AxiDac7654Spi.rtl Architecture Reference

Architecture >> AxiDac7654Spi::rtl

Processes
PROCESS_201	( axiClk )

Constants
AXI_CLK_PERIOD_C	real := 1 . 0 / AXI_CLK_FREQ_G
MAX_CNT_C	natural := getTimeRatio ( 166 . 4E - 9 , AXI_CLK_PERIOD_C )

Types
StateType	( RST_S , IDLE_S , SCK_LOW_S , SCK_HIGH_S , LOAD_S , TLD2_WAIT_S , LDAC_S , HANDSHAKE_S )

Signals
state	StateType := RST_S
ack	sl := ' 0 '
cs	sl := ' 0 '
sck	sl := ' 0 '
sdi	sl := ' 0 '
load	sl := ' 0 '
ldac	sl := ' 0 '
rst	sl := ' 0 '
ch	slv ( 1 downto 0 ) := ( others = > ' 0 ' )
pntr	natural range 0 to 23 := 0
cnt	natural range 0 to MAX_CNT_C := 0

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The documentation for this design unit was generated from the following file:

• devices/Ti/dac7654/rtl/AxiDac7654Spi.vhd