AxiDac7654Core Entity Reference

Inheritance diagram for AxiDac7654Core:

Collaboration diagram for AxiDac7654Core:

Entities
AxiDac7654Core.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>
AxiDac7654Pkg	Package <AxiDac7654Pkg>

Generics
TPD_G	time := 1 ns
AXI_CLK_FREQ_G	real := 125 . 0E + 6
STATUS_CNT_WIDTH_G	natural range 1 to 32 := 32

Ports
dacIn	in	AxiDac7654InType
dacOut	out	AxiDac7654OutType
axiClk	in	sl
axiRst	in	sl
axiReadMaster	in	AxiLiteReadMasterType
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType
axiWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following file:

• devices/Ti/dac7654/rtl/AxiDac7654Core.vhd