AxiAds42lb69Deser Entity Reference

Inheritance diagram for AxiAds42lb69Deser:

Collaboration diagram for AxiAds42lb69Deser:

Entities
AxiAds42lb69Deser.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
std_logic_unsigned
std_logic_arith
StdRtlPkg	Package <StdRtlPkg>
AxiAds42lb69Pkg	Package <AxiAds42lb69Pkg>
vcomponents

Generics
TPD_G	time := 1 ns
USE_PLL_G	boolean := false
USE_FBCLK_G	boolean := true
ADC_CLK_FREQ_G	real := 250 . 0E + 6
DELAY_INIT_G	Slv9VectorArray ( 1 downto 0 , 7 downto 0 ) := ( others = > ( others = > ( others = > ' 0 ' ) ) )
IODELAY_GROUP_G	string := " AXI_ADS42LB69_IODELAY_GRP "
XIL_DEVICE_G	string := " 7SERIES "

Ports
clkP	out	sl
clkN	out	sl
syncP	out	sl
syncN	out	sl
clkFbP	in	sl
clkFbN	in	sl
dataP	in	Slv8Array ( 1 downto 0 )
dataN	in	Slv8Array ( 1 downto 0 )
adcData	out	Slv16Array ( 1 downto 0 )
dmode	in	slv ( 1 downto 0 )
delayIn	in	AxiAds42lb69DelayInType
delayOut	out	AxiAds42lb69DelayOutType
axiClk	in	sl
axiRst	in	sl
adcClk	in	sl
adcRst	in	sl
adcSync	in	sl
refClk200MHz	in	sl
refRst200MHz	in	sl

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The documentation for this design unit was generated from the following file:

• devices/Ti/ads42lb69/rtl/AxiAds42lb69Deser.vhd