AxiAd5541Core Entity Reference

Inheritance diagram for AxiAd5541Core:

Collaboration diagram for AxiAd5541Core:

Entities
AxiAd5541Core.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
numeric_std
StdRtlPkg	Package <StdRtlPkg>
AxiLitePkg	Package <AxiLitePkg>

Generics
TPD_G	time := 1 ns
AXIL_CLK_PERIOD_G	real := 1 / ( 200 . 0E + 6 )
SPI_SCLK_PERIOD_G	real := 1 / ( 1 . 0E + 6 )

Ports
dacSclk	out	sl
dacSdi	out	sl
dacCsL	out	sl
dacLdacL	out	sl
axiClk	in	sl
axiRst	in	sl
axiReadMaster	in	AxiLiteReadMasterType
axiReadSlave	out	AxiLiteReadSlaveType
axiWriteMaster	in	AxiLiteWriteMasterType
axiWriteSlave	out	AxiLiteWriteSlaveType

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/ad5541/rtl/AxiAd5541Core.vhd