AdcDdrPhyUltraScale.rtl Architecture Reference

Architecture >> AdcDdrPhyUltraScale::rtl

Constants
ISERDES_WIDTH_C	positive := ite ( SERIALIZATION_FACTOR_G< = 6 , 4 , 8 )

Signals
bitClk	sl
bitClkInv	sl
wordClk	sl
wordRst	sl
deserReset	sl
fcoPad	slv ( FCO_LANES_G- 1 downto 0 )
dataPad	slv ( DATA_LANES_G- 1 downto 0 )

Instantiations
u_dcoinput	ibufgds
u_wordclock	bufgce_div
u_wordreset	RstSync <Entity RstSync>
u_input	ibufds
u_deserializer	AdcDdrDeserializerUltraScale <Entity AdcDdrDeserializerUltraScale>
u_input	ibufds
u_deserializer	AdcDdrDeserializerUltraScale <Entity AdcDdrDeserializerUltraScale>

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/adcDdr/UltraScale/rtl/AdcDdrPhyUltraScale.vhd