Ad9249Deserializer Entity Reference

Inheritance diagram for Ad9249Deserializer:

Collaboration diagram for Ad9249Deserializer:

Entities
Ad9249Deserializer.rtl	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>
vcomponents
std_logic_arith
std_logic_unsigned
AxiLitePkg	Package <AxiLitePkg>
AxiStreamPkg	Package <AxiStreamPkg>
Ad9249Pkg	Package <Ad9249Pkg>

Generics
TPD_G	time := 1 ns
IODELAY_GROUP_G	string
IDELAYCTRL_FREQ_G	real := 200 . 0
SIM_DEVICE_G	string := " ULTRASCALE "
IDELAY_CASCADE_G	boolean := false
DEFAULT_DELAY_G	slv ( 8 downto 0 ) := ( others = > ' 0 ' )
ADC_INVERT_CH_G	sl := ' 0 '
BIT_REV_G	sl := ' 0 '

Ports
clkIo	in	sl
clkIoInv	in	sl
clkR	in	sl
rst	in	sl
slip	in	sl
sysClk	in	sl
curDelay	out	slv ( 4 downto 0 )
setDelay	in	slv ( 4 downto 0 )
setValid	in	sl
iData	in	sl
oData	out	slv ( 13 downto 0 )
dClk	in	sl
dRst	in	sl
dClkDiv4	in	sl
dRstDiv4	in	sl
sDataP	in	sl
sDataN	in	sl
loadDelay	in	sl
delay	in	slv ( 8 downto 0 ) := " 000000000 "
delayValueOut	out	slv ( 8 downto 0 )
bitSlip	in	sl
adcData	out	slv ( 13 downto 0 )
adcValid	out	sl

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The documentation for this design unit was generated from the following files:

• devices/AnalogDevices/ad9249/7Series/rtl/Ad9249Deserializer.vhd
• devices/AnalogDevices/ad9249/UltraScale/rtl/Ad9249Deserializer.vhd