Ad9249ConfigNoPullup.rtl Architecture Reference

Architecture >> Ad9249ConfigNoPullup::rtl

Processes
comb	( adcAck , adcRdData , axilReadMaster , axilRst , axilWriteMaster , r )
seq	( axilClk )
PROCESS_185	( axilClk )
PROCESS_186	( axilClk )
PROCESS_187	( adcRdReq , adcWrReq , curState , shiftCntEn )

Constants
SPI_CLK_PERIOD_DIV2_CYCLES_C	integer := integer ( CLK_EN_PERIOD_G/ CLK_PERIOD_G ) / 2
SCLK_COUNTER_SIZE_C	integer := bitSize ( SPI_CLK_PERIOD_DIV2_CYCLES_C )
ST_IDLE	std_logic_vector ( 1 downto 0 ) := " 01 "
ST_SHIFT	std_logic_vector ( 1 downto 0 ) := " 10 "
ST_DONE	std_logic_vector ( 1 downto 0 ) := " 11 "
CHIP_SEL_WIDTH_C	integer := log2 ( NUM_CHIPS_G* 2 )
PWDN_ADDR_BIT_C	integer := 11 + CHIP_SEL_WIDTH_C
PWDN_ADDR_C	slv ( PWDN_ADDR_BIT_C downto 0 ) := toSlv ( 2 ** PWDN_ADDR_BIT_C , PWDN_ADDR_BIT_C+ 1 )
REG_INIT_C	RegType := ( state = > ADC_IDLE_S , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , chipSel = > ( others = > ' 0 ' ) , wrData = > ( others = > ' 0 ' ) , adcWrReq = > ' 0 ' , adcRdReq = > ' 0 ' , pdwn = > ( others = > ' 0 ' ) )

Types
StateType	( ADC_IDLE_S , ADC_READ_S , ADC_WRITE_S )

Signals
intShift	std_logic_vector ( 23 downto 0 )
nextClk	std_logic
nextAck	std_logic
shiftCnt	std_logic_vector ( 12 downto 0 )
shiftCntEn	std_logic
shiftEn	std_logic
locSDout	std_logic
adcSDir	std_logic
axilClkEn	std_logic
sclkCounter	std_logic_vector ( SCLK_COUNTER_SIZE_C- 1 downto 0 )
curState	std_logic_vector ( 1 downto 0 )
nxtState	std_logic_vector ( 1 downto 0 )
adcWrData	std_logic_vector ( 7 downto 0 )
adcRdData	std_logic_vector ( 7 downto 0 )
adcAddr	std_logic_vector ( 12 downto 0 )
adcWrReq	std_logic
adcRdReq	std_logic
adcAck	std_logic
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following file:

• devices/AnalogDevices/ad9249/7Series/rtl/Ad9249ConfigNoPullup.vhd