SURF  1.0
Ports | Libraries | Use Clauses
XauiGth7Core Entity Reference
ethernet » XauiCore » gth7
+ Inheritance diagram for XauiGth7Core:

Entities

wrapper  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 

Ports

dclk   in std_logic
reset   in std_logic
clk156_out   out std_logic
clk156_lock   out std_logic
refclk   in std_logic
xgmii_txd   in std_logic_vector ( 63 downto 0 )
xgmii_txc   in std_logic_vector ( 7 downto 0 )
xgmii_rxd   out std_logic_vector ( 63 downto 0 )
xgmii_rxc   out std_logic_vector ( 7 downto 0 )
xaui_tx_l0_p   out std_logic
xaui_tx_l0_n   out std_logic
xaui_tx_l1_p   out std_logic
xaui_tx_l1_n   out std_logic
xaui_tx_l2_p   out std_logic
xaui_tx_l2_n   out std_logic
xaui_tx_l3_p   out std_logic
xaui_tx_l3_n   out std_logic
xaui_rx_l0_p   in std_logic
xaui_rx_l0_n   in std_logic
xaui_rx_l1_p   in std_logic
xaui_rx_l1_n   in std_logic
xaui_rx_l2_p   in std_logic
xaui_rx_l2_n   in std_logic
xaui_rx_l3_p   in std_logic
xaui_rx_l3_n   in std_logic
signal_detect   in std_logic_vector ( 3 downto 0 )
debug   out std_logic_vector ( 5 downto 0 )
configuration_vector   in std_logic_vector ( 6 downto 0 )
status_vector   out std_logic_vector ( 7 downto 0 )

Detailed Description

See also
entity

Definition at line 23 of file XauiGth7Core.vhd.

Member Data Documentation

◆ dclk

dclk in std_logic
Port

Definition at line 25 of file XauiGth7Core.vhd.

◆ reset

reset in std_logic
Port

Definition at line 26 of file XauiGth7Core.vhd.

◆ clk156_out

clk156_out out std_logic
Port

Definition at line 27 of file XauiGth7Core.vhd.

◆ clk156_lock

clk156_lock out std_logic
Port

Definition at line 28 of file XauiGth7Core.vhd.

◆ refclk

refclk in std_logic
Port

Definition at line 29 of file XauiGth7Core.vhd.

◆ xgmii_txd

xgmii_txd in std_logic_vector ( 63 downto 0 )
Port

Definition at line 30 of file XauiGth7Core.vhd.

◆ xgmii_txc

xgmii_txc in std_logic_vector ( 7 downto 0 )
Port

Definition at line 31 of file XauiGth7Core.vhd.

◆ xgmii_rxd

xgmii_rxd out std_logic_vector ( 63 downto 0 )
Port

Definition at line 32 of file XauiGth7Core.vhd.

◆ xgmii_rxc

xgmii_rxc out std_logic_vector ( 7 downto 0 )
Port

Definition at line 33 of file XauiGth7Core.vhd.

◆ xaui_tx_l0_p

xaui_tx_l0_p out std_logic
Port

Definition at line 34 of file XauiGth7Core.vhd.

◆ xaui_tx_l0_n

xaui_tx_l0_n out std_logic
Port

Definition at line 35 of file XauiGth7Core.vhd.

◆ xaui_tx_l1_p

xaui_tx_l1_p out std_logic
Port

Definition at line 36 of file XauiGth7Core.vhd.

◆ xaui_tx_l1_n

xaui_tx_l1_n out std_logic
Port

Definition at line 37 of file XauiGth7Core.vhd.

◆ xaui_tx_l2_p

xaui_tx_l2_p out std_logic
Port

Definition at line 38 of file XauiGth7Core.vhd.

◆ xaui_tx_l2_n

xaui_tx_l2_n out std_logic
Port

Definition at line 39 of file XauiGth7Core.vhd.

◆ xaui_tx_l3_p

xaui_tx_l3_p out std_logic
Port

Definition at line 40 of file XauiGth7Core.vhd.

◆ xaui_tx_l3_n

xaui_tx_l3_n out std_logic
Port

Definition at line 41 of file XauiGth7Core.vhd.

◆ xaui_rx_l0_p

xaui_rx_l0_p in std_logic
Port

Definition at line 42 of file XauiGth7Core.vhd.

◆ xaui_rx_l0_n

xaui_rx_l0_n in std_logic
Port

Definition at line 43 of file XauiGth7Core.vhd.

◆ xaui_rx_l1_p

xaui_rx_l1_p in std_logic
Port

Definition at line 44 of file XauiGth7Core.vhd.

◆ xaui_rx_l1_n

xaui_rx_l1_n in std_logic
Port

Definition at line 45 of file XauiGth7Core.vhd.

◆ xaui_rx_l2_p

xaui_rx_l2_p in std_logic
Port

Definition at line 46 of file XauiGth7Core.vhd.

◆ xaui_rx_l2_n

xaui_rx_l2_n in std_logic
Port

Definition at line 47 of file XauiGth7Core.vhd.

◆ xaui_rx_l3_p

xaui_rx_l3_p in std_logic
Port

Definition at line 48 of file XauiGth7Core.vhd.

◆ xaui_rx_l3_n

xaui_rx_l3_n in std_logic
Port

Definition at line 49 of file XauiGth7Core.vhd.

◆ signal_detect

signal_detect in std_logic_vector ( 3 downto 0 )
Port

Definition at line 50 of file XauiGth7Core.vhd.

◆ debug

debug out std_logic_vector ( 5 downto 0 )
Port

Definition at line 51 of file XauiGth7Core.vhd.

◆ configuration_vector

configuration_vector in std_logic_vector ( 6 downto 0 )
Port

Definition at line 52 of file XauiGth7Core.vhd.

◆ status_vector

status_vector out std_logic_vector ( 7 downto 0 )
Port

Definition at line 54 of file XauiGth7Core.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file XauiGth7Core.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file XauiGth7Core.vhd.

The documentation for this class was generated from the following file: