SURF  1.0
XauiGth7Core.vhd
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1 -------------------------------------------------------------------------------
2 -- File : XauiGth7Core.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2015-02-12
5 -- Last update: 2016-02-19
6 -------------------------------------------------------------------------------
7 -- Description: 10 GigE XAUI for Gth7 Core
8 -------------------------------------------------------------------------------
9 -- This file is part of 'SLAC Firmware Standard Library'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'SLAC Firmware Standard Library', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 
21 --! @see entity
22  --! @ingroup ethernet_XauiCore_gth7
23 entity XauiGth7Core is
24  port (
25  dclk : in std_logic;
26  reset : in std_logic;
27  clk156_out : out std_logic;
28  clk156_lock : out std_logic;
29  refclk : in std_logic;
30  xgmii_txd : in std_logic_vector(63 downto 0);
31  xgmii_txc : in std_logic_vector(7 downto 0);
32  xgmii_rxd : out std_logic_vector(63 downto 0);
33  xgmii_rxc : out std_logic_vector(7 downto 0);
34  xaui_tx_l0_p : out std_logic;
35  xaui_tx_l0_n : out std_logic;
36  xaui_tx_l1_p : out std_logic;
37  xaui_tx_l1_n : out std_logic;
38  xaui_tx_l2_p : out std_logic;
39  xaui_tx_l2_n : out std_logic;
40  xaui_tx_l3_p : out std_logic;
41  xaui_tx_l3_n : out std_logic;
42  xaui_rx_l0_p : in std_logic;
43  xaui_rx_l0_n : in std_logic;
44  xaui_rx_l1_p : in std_logic;
45  xaui_rx_l1_n : in std_logic;
46  xaui_rx_l2_p : in std_logic;
47  xaui_rx_l2_n : in std_logic;
48  xaui_rx_l3_p : in std_logic;
49  xaui_rx_l3_n : in std_logic;
50  signal_detect : in std_logic_vector(3 downto 0);
51  debug : out std_logic_vector(5 downto 0); -- Debug vector
52  configuration_vector : in std_logic_vector(6 downto 0);
53  status_vector : out std_logic_vector(7 downto 0)
54 );
55 end XauiGth7Core;
56 
57 library xaui_v12_1;
58 use xaui_v12_1.all;
59 
60 architecture wrapper of XauiGth7Core is
61 
62  component XauiGth7Core_block is
63  port (
64  dclk : in std_logic;
65  reset : in std_logic;
66  clk156_out : out std_logic;
67  clk156_lock : out std_logic;
68  refclk : in std_logic;
69  xgmii_txd : in std_logic_vector(63 downto 0);
70  xgmii_txc : in std_logic_vector(7 downto 0);
71  xgmii_rxd : out std_logic_vector(63 downto 0);
72  xgmii_rxc : out std_logic_vector(7 downto 0);
73  xaui_tx_l0_p : out std_logic;
74  xaui_tx_l0_n : out std_logic;
75  xaui_tx_l1_p : out std_logic;
76  xaui_tx_l1_n : out std_logic;
77  xaui_tx_l2_p : out std_logic;
78  xaui_tx_l2_n : out std_logic;
79  xaui_tx_l3_p : out std_logic;
80  xaui_tx_l3_n : out std_logic;
81  xaui_rx_l0_p : in std_logic;
82  xaui_rx_l0_n : in std_logic;
83  xaui_rx_l1_p : in std_logic;
84  xaui_rx_l1_n : in std_logic;
85  xaui_rx_l2_p : in std_logic;
86  xaui_rx_l2_n : in std_logic;
87  xaui_rx_l3_p : in std_logic;
88  xaui_rx_l3_n : in std_logic;
89  signal_detect : in std_logic_vector(3 downto 0);
90  debug : out std_logic_vector(5 downto 0); -- Debug vector
91  -- GT Control Ports
92  -- DRP
93  gt0_drpaddr : in std_logic_vector(8 downto 0);
94  gt0_drpen : in std_logic;
95  gt0_drpdi : in std_logic_vector(15 downto 0);
96  gt0_drpdo : out std_logic_vector(15 downto 0);
97  gt0_drprdy : out std_logic;
98  gt0_drpwe : in std_logic;
99  gt0_drp_busy : out std_logic;
100  -- TX Reset and Initialisation
101  gt0_txpmareset_in : in std_logic;
102  gt0_txpcsreset_in : in std_logic;
103  gt0_txresetdone_out : out std_logic;
104  -- RX Reset and Initialisation
105  gt0_rxpmareset_in : in std_logic;
106  gt0_rxpcsreset_in : in std_logic;
107  gt0_rxpmaresetdone_out : out std_logic;
108  gt0_rxresetdone_out : out std_logic;
109  -- Clocking
110  gt0_rxbufstatus_out : out std_logic_vector(2 downto 0);
111  gt0_txphaligndone_out : out std_logic;
112  gt0_txphinitdone_out : out std_logic;
113  gt0_txdlysresetdone_out : out std_logic;
114  gt0_cplllock_out : out std_logic;
115  -- Signal Integrity adn Functionality
116  -- Eye Scan
117  gt0_eyescantrigger_in : in std_logic;
118  gt0_eyescanreset_in : in std_logic;
119  gt0_eyescandataerror_out : out std_logic;
120  gt0_rxrate_in : in std_logic_vector(2 downto 0);
121  -- Loopback
122  gt0_loopback_in : in std_logic_vector(2 downto 0);
123  -- Polarity
124  gt0_rxpolarity_in : in std_logic;
125  gt0_txpolarity_in : in std_logic;
126  -- RX Decision Feedback Equalizer(DFE)
127  gt0_rxlpmen_in : in std_logic;
128  gt0_rxdfelpmreset_in : in std_logic;
129  gt0_rxmonitorsel_in : in std_logic_vector(1 downto 0);
130  gt0_rxmonitorout_out : out std_logic_vector(6 downto 0);
131  -- TX Driver
132  gt0_txpostcursor_in : in std_logic_vector(4 downto 0);
133  gt0_txprecursor_in : in std_logic_vector(4 downto 0);
134  gt0_txdiffctrl_in : in std_logic_vector(3 downto 0);
135  -- PRBS
136  gt0_rxprbscntreset_in : in std_logic;
137  gt0_rxprbserr_out : out std_logic;
138  gt0_rxprbssel_in : in std_logic_vector(2 downto 0);
139  gt0_txprbssel_in : in std_logic_vector(2 downto 0);
140  gt0_txprbsforceerr_in : in std_logic;
141 
142  gt0_rxcdrhold_in : in std_logic;
143 
144  gt0_dmonitorout_out : out std_logic_vector(14 downto 0);
145 
146  -- Status
147  gt0_rxdisperr_out : out std_logic_vector(1 downto 0);
148  gt0_rxnotintable_out : out std_logic_vector(1 downto 0);
149  gt0_rxcommadet_out : out std_logic;
150  -- DRP
151  gt1_drpaddr : in std_logic_vector(8 downto 0);
152  gt1_drpen : in std_logic;
153  gt1_drpdi : in std_logic_vector(15 downto 0);
154  gt1_drpdo : out std_logic_vector(15 downto 0);
155  gt1_drprdy : out std_logic;
156  gt1_drpwe : in std_logic;
157  gt1_drp_busy : out std_logic;
158  -- TX Reset and Initialisation
159  gt1_txpmareset_in : in std_logic;
160  gt1_txpcsreset_in : in std_logic;
161  gt1_txresetdone_out : out std_logic;
162  -- RX Reset and Initialisation
163  gt1_rxpmareset_in : in std_logic;
164  gt1_rxpcsreset_in : in std_logic;
165  gt1_rxpmaresetdone_out : out std_logic;
166  gt1_rxresetdone_out : out std_logic;
167  -- Clocking
168  gt1_rxbufstatus_out : out std_logic_vector(2 downto 0);
169  gt1_txphaligndone_out : out std_logic;
170  gt1_txphinitdone_out : out std_logic;
171  gt1_txdlysresetdone_out : out std_logic;
172  gt1_cplllock_out : out std_logic;
173  -- Signal Integrity adn Functionality
174  -- Eye Scan
175  gt1_eyescantrigger_in : in std_logic;
176  gt1_eyescanreset_in : in std_logic;
177  gt1_eyescandataerror_out : out std_logic;
178  gt1_rxrate_in : in std_logic_vector(2 downto 0);
179  -- Loopback
180  gt1_loopback_in : in std_logic_vector(2 downto 0);
181  -- Polarity
182  gt1_rxpolarity_in : in std_logic;
183  gt1_txpolarity_in : in std_logic;
184  -- RX Decision Feedback Equalizer(DFE)
185  gt1_rxlpmen_in : in std_logic;
186  gt1_rxdfelpmreset_in : in std_logic;
187  gt1_rxmonitorsel_in : in std_logic_vector(1 downto 0);
188  gt1_rxmonitorout_out : out std_logic_vector(6 downto 0);
189  -- TX Driver
190  gt1_txpostcursor_in : in std_logic_vector(4 downto 0);
191  gt1_txprecursor_in : in std_logic_vector(4 downto 0);
192  gt1_txdiffctrl_in : in std_logic_vector(3 downto 0);
193  -- PRBS
194  gt1_rxprbscntreset_in : in std_logic;
195  gt1_rxprbserr_out : out std_logic;
196  gt1_rxprbssel_in : in std_logic_vector(2 downto 0);
197  gt1_txprbssel_in : in std_logic_vector(2 downto 0);
198  gt1_txprbsforceerr_in : in std_logic;
199 
200  gt1_rxcdrhold_in : in std_logic;
201 
202  gt1_dmonitorout_out : out std_logic_vector(14 downto 0);
203 
204  -- Status
205  gt1_rxdisperr_out : out std_logic_vector(1 downto 0);
206  gt1_rxnotintable_out : out std_logic_vector(1 downto 0);
207  gt1_rxcommadet_out : out std_logic;
208  -- DRP
209  gt2_drpaddr : in std_logic_vector(8 downto 0);
210  gt2_drpen : in std_logic;
211  gt2_drpdi : in std_logic_vector(15 downto 0);
212  gt2_drpdo : out std_logic_vector(15 downto 0);
213  gt2_drprdy : out std_logic;
214  gt2_drpwe : in std_logic;
215  gt2_drp_busy : out std_logic;
216  -- TX Reset and Initialisation
217  gt2_txpmareset_in : in std_logic;
218  gt2_txpcsreset_in : in std_logic;
219  gt2_txresetdone_out : out std_logic;
220  -- RX Reset and Initialisation
221  gt2_rxpmareset_in : in std_logic;
222  gt2_rxpcsreset_in : in std_logic;
223  gt2_rxpmaresetdone_out : out std_logic;
224  gt2_rxresetdone_out : out std_logic;
225  -- Clocking
226  gt2_rxbufstatus_out : out std_logic_vector(2 downto 0);
227  gt2_txphaligndone_out : out std_logic;
228  gt2_txphinitdone_out : out std_logic;
229  gt2_txdlysresetdone_out : out std_logic;
230  gt2_cplllock_out : out std_logic;
231  -- Signal Integrity adn Functionality
232  -- Eye Scan
233  gt2_eyescantrigger_in : in std_logic;
234  gt2_eyescanreset_in : in std_logic;
235  gt2_eyescandataerror_out : out std_logic;
236  gt2_rxrate_in : in std_logic_vector(2 downto 0);
237  -- Loopback
238  gt2_loopback_in : in std_logic_vector(2 downto 0);
239  -- Polarity
240  gt2_rxpolarity_in : in std_logic;
241  gt2_txpolarity_in : in std_logic;
242  -- RX Decision Feedback Equalizer(DFE)
243  gt2_rxlpmen_in : in std_logic;
244  gt2_rxdfelpmreset_in : in std_logic;
245  gt2_rxmonitorsel_in : in std_logic_vector(1 downto 0);
246  gt2_rxmonitorout_out : out std_logic_vector(6 downto 0);
247  -- TX Driver
248  gt2_txpostcursor_in : in std_logic_vector(4 downto 0);
249  gt2_txprecursor_in : in std_logic_vector(4 downto 0);
250  gt2_txdiffctrl_in : in std_logic_vector(3 downto 0);
251  -- PRBS
252  gt2_rxprbscntreset_in : in std_logic;
253  gt2_rxprbserr_out : out std_logic;
254  gt2_rxprbssel_in : in std_logic_vector(2 downto 0);
255  gt2_txprbssel_in : in std_logic_vector(2 downto 0);
256  gt2_txprbsforceerr_in : in std_logic;
257 
258  gt2_rxcdrhold_in : in std_logic;
259 
260  gt2_dmonitorout_out : out std_logic_vector(14 downto 0);
261 
262  -- Status
263  gt2_rxdisperr_out : out std_logic_vector(1 downto 0);
264  gt2_rxnotintable_out : out std_logic_vector(1 downto 0);
265  gt2_rxcommadet_out : out std_logic;
266  -- DRP
267  gt3_drpaddr : in std_logic_vector(8 downto 0);
268  gt3_drpen : in std_logic;
269  gt3_drpdi : in std_logic_vector(15 downto 0);
270  gt3_drpdo : out std_logic_vector(15 downto 0);
271  gt3_drprdy : out std_logic;
272  gt3_drpwe : in std_logic;
273  gt3_drp_busy : out std_logic;
274  -- TX Reset and Initialisation
275  gt3_txpmareset_in : in std_logic;
276  gt3_txpcsreset_in : in std_logic;
277  gt3_txresetdone_out : out std_logic;
278  -- RX Reset and Initialisation
279  gt3_rxpmareset_in : in std_logic;
280  gt3_rxpcsreset_in : in std_logic;
281  gt3_rxpmaresetdone_out : out std_logic;
282  gt3_rxresetdone_out : out std_logic;
283  -- Clocking
284  gt3_rxbufstatus_out : out std_logic_vector(2 downto 0);
285  gt3_txphaligndone_out : out std_logic;
286  gt3_txphinitdone_out : out std_logic;
287  gt3_txdlysresetdone_out : out std_logic;
288  gt3_cplllock_out : out std_logic;
289  -- Signal Integrity adn Functionality
290  -- Eye Scan
291  gt3_eyescantrigger_in : in std_logic;
292  gt3_eyescanreset_in : in std_logic;
293  gt3_eyescandataerror_out : out std_logic;
294  gt3_rxrate_in : in std_logic_vector(2 downto 0);
295  -- Loopback
296  gt3_loopback_in : in std_logic_vector(2 downto 0);
297  -- Polarity
298  gt3_rxpolarity_in : in std_logic;
299  gt3_txpolarity_in : in std_logic;
300  -- RX Decision Feedback Equalizer(DFE)
301  gt3_rxlpmen_in : in std_logic;
302  gt3_rxdfelpmreset_in : in std_logic;
303  gt3_rxmonitorsel_in : in std_logic_vector(1 downto 0);
304  gt3_rxmonitorout_out : out std_logic_vector(6 downto 0);
305  -- TX Driver
306  gt3_txpostcursor_in : in std_logic_vector(4 downto 0);
307  gt3_txprecursor_in : in std_logic_vector(4 downto 0);
308  gt3_txdiffctrl_in : in std_logic_vector(3 downto 0);
309  -- PRBS
310  gt3_rxprbscntreset_in : in std_logic;
311  gt3_rxprbserr_out : out std_logic;
312  gt3_rxprbssel_in : in std_logic_vector(2 downto 0);
313  gt3_txprbssel_in : in std_logic_vector(2 downto 0);
314  gt3_txprbsforceerr_in : in std_logic;
315 
316  gt3_rxcdrhold_in : in std_logic;
317 
318  gt3_dmonitorout_out : out std_logic_vector(14 downto 0);
319 
320  -- Status
321  gt3_rxdisperr_out : out std_logic_vector(1 downto 0);
322  gt3_rxnotintable_out : out std_logic_vector(1 downto 0);
323  gt3_rxcommadet_out : out std_logic;
324  configuration_vector : in std_logic_vector(6 downto 0);
325  status_vector : out std_logic_vector(7 downto 0)
326 );
327  end component;
328 
329  ATTRIBUTE CORE_GENERATION_INFO : STRING;
330  ATTRIBUTE CORE_GENERATION_INFO OF wrapper : ARCHITECTURE IS "XauiGth7Core,xaui_v12_1,{x_ipProduct=Vivado 2014.4.1,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=xaui,x_ipVersion=12.1,x_ipCoreRevision=4,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,c_family=virtex7,c_component_name=XauiGth7Core,c_is_dxaui=false,c_has_mdio=false,c_sub_core_name=XauiGth7Core_gt,c_gt_dmonitorout_width=15,c_gt_txdiffctrl_width=16}";
331  ATTRIBUTE X_CORE_INFO : STRING;
332  ATTRIBUTE X_CORE_INFO OF wrapper: ARCHITECTURE IS "xaui_v12_1,Vivado 2014.4.1";
333 
334 begin
335 
336  U0 : XauiGth7Core_block
337  port map(
338  dclk => dclk,
339  reset => reset,
340  clk156_out => clk156_out,
341  clk156_lock => clk156_lock,
342  refclk => refclk,
343  xgmii_txd => xgmii_txd,
344  xgmii_txc => xgmii_txc,
345  xgmii_rxd => xgmii_rxd,
346  xgmii_rxc => xgmii_rxc,
347  xaui_tx_l0_p => xaui_tx_l0_p,
348  xaui_tx_l0_n => xaui_tx_l0_n,
349  xaui_tx_l1_p => xaui_tx_l1_p,
350  xaui_tx_l1_n => xaui_tx_l1_n,
351  xaui_tx_l2_p => xaui_tx_l2_p,
352  xaui_tx_l2_n => xaui_tx_l2_n,
353  xaui_tx_l3_p => xaui_tx_l3_p,
354  xaui_tx_l3_n => xaui_tx_l3_n,
355  xaui_rx_l0_p => xaui_rx_l0_p,
356  xaui_rx_l0_n => xaui_rx_l0_n,
357  xaui_rx_l1_p => xaui_rx_l1_p,
358  xaui_rx_l1_n => xaui_rx_l1_n,
359  xaui_rx_l2_p => xaui_rx_l2_p,
360  xaui_rx_l2_n => xaui_rx_l2_n,
361  xaui_rx_l3_p => xaui_rx_l3_p,
362  xaui_rx_l3_n => xaui_rx_l3_n,
363  signal_detect => signal_detect,
364  debug => debug,
365  -- DRP
366  gt0_drpaddr => (others => '0'),
367  gt0_drpen => '0',
368  gt0_drpdi => (others => '0'),
369  gt0_drpdo => open,
370  gt0_drprdy => open,
371  gt0_drpwe => '0',
372  gt0_drp_busy => open,
373  -- TX Reset and Initialisation
374  gt0_txpmareset_in => '0',
375  gt0_txpcsreset_in => '0',
376  gt0_txresetdone_out => open,
377  -- RX Reset and Initialisation
378  gt0_rxpmareset_in => '0',
379  gt0_rxpcsreset_in => '0',
380  gt0_rxpmaresetdone_out => open,
381  gt0_rxresetdone_out => open,
382  -- Clocking
383  gt0_rxbufstatus_out => open,
384  gt0_txphaligndone_out => open,
385  gt0_txphinitdone_out => open,
386  gt0_txdlysresetdone_out => open,
387  gt0_cplllock_out => open,
388  -- Signal Integrity adn Functionality
389  -- Eye Scan
390  gt0_eyescantrigger_in => '0',
391  gt0_eyescanreset_in => '0',
392  gt0_eyescandataerror_out => open,
393  gt0_rxrate_in => "000",
394  -- Loopback
395  gt0_loopback_in => "000",
396  -- Polarity
397  gt0_rxpolarity_in => '0',
398  gt0_txpolarity_in => '0',
399  -- RX Decision Feedback Equalizer(DFE)
400  gt0_rxlpmen_in => '0',
401  gt0_rxdfelpmreset_in => '0',
402  gt0_rxmonitorsel_in => "00",
403  gt0_rxmonitorout_out => open,
404  -- TX Driver
405  gt0_txdiffctrl_in => "1000",
406  gt0_txpostcursor_in => "00000",
407  gt0_txprecursor_in => "00000",
408  -- PRBS - GT
409  gt0_rxprbscntreset_in => '0',
410  gt0_rxprbserr_out => open,
411  gt0_rxprbssel_in => "000",
412  gt0_txprbssel_in => "000",
413  gt0_txprbsforceerr_in => '0',
414 
415  gt0_rxcdrhold_in => '0',
416 
417  gt0_dmonitorout_out => open,
418 
419  -- Status
420  gt0_rxdisperr_out => open,
421  gt0_rxnotintable_out => open,
422  gt0_rxcommadet_out => open,
423  -- DRP
424  gt1_drpaddr => (others => '0'),
425  gt1_drpen => '0',
426  gt1_drpdi => (others => '0'),
427  gt1_drpdo => open,
428  gt1_drprdy => open,
429  gt1_drpwe => '0',
430  gt1_drp_busy => open,
431  -- TX Reset and Initialisation
432  gt1_txpmareset_in => '0',
433  gt1_txpcsreset_in => '0',
434  gt1_txresetdone_out => open,
435  -- RX Reset and Initialisation
436  gt1_rxpmareset_in => '0',
437  gt1_rxpcsreset_in => '0',
438  gt1_rxpmaresetdone_out => open,
439  gt1_rxresetdone_out => open,
440  -- Clocking
441  gt1_rxbufstatus_out => open,
442  gt1_txphaligndone_out => open,
443  gt1_txphinitdone_out => open,
444  gt1_txdlysresetdone_out => open,
445  gt1_cplllock_out => open,
446  -- Signal Integrity adn Functionality
447  -- Eye Scan
448  gt1_eyescantrigger_in => '0',
449  gt1_eyescanreset_in => '0',
450  gt1_eyescandataerror_out => open,
451  gt1_rxrate_in => "000",
452  -- Loopback
453  gt1_loopback_in => "000",
454  -- Polarity
455  gt1_rxpolarity_in => '0',
456  gt1_txpolarity_in => '0',
457  -- RX Decision Feedback Equalizer(DFE)
458  gt1_rxlpmen_in => '0',
459  gt1_rxdfelpmreset_in => '0',
460  gt1_rxmonitorsel_in => "00",
461  gt1_rxmonitorout_out => open,
462  -- TX Driver
463  gt1_txdiffctrl_in => "1000",
464  gt1_txpostcursor_in => "00000",
465  gt1_txprecursor_in => "00000",
466  -- PRBS - GT
467  gt1_rxprbscntreset_in => '0',
468  gt1_rxprbserr_out => open,
469  gt1_rxprbssel_in => "000",
470  gt1_txprbssel_in => "000",
471  gt1_txprbsforceerr_in => '0',
472 
473  gt1_rxcdrhold_in => '0',
474 
475  gt1_dmonitorout_out => open,
476 
477  -- Status
478  gt1_rxdisperr_out => open,
479  gt1_rxnotintable_out => open,
480  gt1_rxcommadet_out => open,
481  -- DRP
482  gt2_drpaddr => (others => '0'),
483  gt2_drpen => '0',
484  gt2_drpdi => (others => '0'),
485  gt2_drpdo => open,
486  gt2_drprdy => open,
487  gt2_drpwe => '0',
488  gt2_drp_busy => open,
489  -- TX Reset and Initialisation
490  gt2_txpmareset_in => '0',
491  gt2_txpcsreset_in => '0',
492  gt2_txresetdone_out => open,
493  -- RX Reset and Initialisation
494  gt2_rxpmareset_in => '0',
495  gt2_rxpcsreset_in => '0',
496  gt2_rxpmaresetdone_out => open,
497  gt2_rxresetdone_out => open,
498  -- Clocking
499  gt2_rxbufstatus_out => open,
500  gt2_txphaligndone_out => open,
501  gt2_txphinitdone_out => open,
502  gt2_txdlysresetdone_out => open,
503  gt2_cplllock_out => open,
504  -- Signal Integrity adn Functionality
505  -- Eye Scan
506  gt2_eyescantrigger_in => '0',
507  gt2_eyescanreset_in => '0',
508  gt2_eyescandataerror_out => open,
509  gt2_rxrate_in => "000",
510  -- Loopback
511  gt2_loopback_in => "000",
512  -- Polarity
513  gt2_rxpolarity_in => '0',
514  gt2_txpolarity_in => '0',
515  -- RX Decision Feedback Equalizer(DFE)
516  gt2_rxlpmen_in => '0',
517  gt2_rxdfelpmreset_in => '0',
518  gt2_rxmonitorsel_in => "00",
519  gt2_rxmonitorout_out => open,
520  -- TX Driver
521  gt2_txdiffctrl_in => "1000",
522  gt2_txpostcursor_in => "00000",
523  gt2_txprecursor_in => "00000",
524  -- PRBS - GT
525  gt2_rxprbscntreset_in => '0',
526  gt2_rxprbserr_out => open,
527  gt2_rxprbssel_in => "000",
528  gt2_txprbssel_in => "000",
529  gt2_txprbsforceerr_in => '0',
530 
531  gt2_rxcdrhold_in => '0',
532 
533  gt2_dmonitorout_out => open,
534 
535  -- Status
536  gt2_rxdisperr_out => open,
537  gt2_rxnotintable_out => open,
538  gt2_rxcommadet_out => open,
539  -- DRP
540  gt3_drpaddr => (others => '0'),
541  gt3_drpen => '0',
542  gt3_drpdi => (others => '0'),
543  gt3_drpdo => open,
544  gt3_drprdy => open,
545  gt3_drpwe => '0',
546  gt3_drp_busy => open,
547  -- TX Reset and Initialisation
548  gt3_txpmareset_in => '0',
549  gt3_txpcsreset_in => '0',
550  gt3_txresetdone_out => open,
551  -- RX Reset and Initialisation
552  gt3_rxpmareset_in => '0',
553  gt3_rxpcsreset_in => '0',
554  gt3_rxpmaresetdone_out => open,
555  gt3_rxresetdone_out => open,
556  -- Clocking
557  gt3_rxbufstatus_out => open,
558  gt3_txphaligndone_out => open,
559  gt3_txphinitdone_out => open,
560  gt3_txdlysresetdone_out => open,
561  gt3_cplllock_out => open,
562  -- Signal Integrity adn Functionality
563  -- Eye Scan
564  gt3_eyescantrigger_in => '0',
565  gt3_eyescanreset_in => '0',
566  gt3_eyescandataerror_out => open,
567  gt3_rxrate_in => "000",
568  -- Loopback
569  gt3_loopback_in => "000",
570  -- Polarity
571  gt3_rxpolarity_in => '0',
572  gt3_txpolarity_in => '0',
573  -- RX Decision Feedback Equalizer(DFE)
574  gt3_rxlpmen_in => '0',
575  gt3_rxdfelpmreset_in => '0',
576  gt3_rxmonitorsel_in => "00",
577  gt3_rxmonitorout_out => open,
578  -- TX Driver
579  gt3_txdiffctrl_in => "1000",
580  gt3_txpostcursor_in => "00000",
581  gt3_txprecursor_in => "00000",
582  -- PRBS - GT
583  gt3_rxprbscntreset_in => '0',
584  gt3_rxprbserr_out => open,
585  gt3_rxprbssel_in => "000",
586  gt3_txprbssel_in => "000",
587  gt3_txprbsforceerr_in => '0',
588 
589  gt3_rxcdrhold_in => '0',
590 
591  gt3_dmonitorout_out => open,
592 
593  -- Status
594  gt3_rxdisperr_out => open,
595  gt3_rxnotintable_out => open,
596  gt3_rxcommadet_out => open,
597  configuration_vector => configuration_vector,
598  status_vector => status_vector
599 );
600 
601 end wrapper;
XauiGth7Core.xaui_rx_l3_n
in xaui_rx_l3_nstd_logic
Definition: XauiGth7Core.vhd:49
XauiGth7Core.xgmii_rxc
out xgmii_rxcstd_logic_vector( 7 downto 0)
Definition: XauiGth7Core.vhd:33
XauiGth7Core.dclk
in dclkstd_logic
Definition: XauiGth7Core.vhd:25
XauiGth7Core.xaui_tx_l0_n
out xaui_tx_l0_nstd_logic
Definition: XauiGth7Core.vhd:35
XauiGth7Core.xgmii_txc
in xgmii_txcstd_logic_vector( 7 downto 0)
Definition: XauiGth7Core.vhd:31
XauiGth7Core.xgmii_txd
in xgmii_txdstd_logic_vector( 63 downto 0)
Definition: XauiGth7Core.vhd:30
XauiGth7Core.xaui_rx_l3_p
in xaui_rx_l3_pstd_logic
Definition: XauiGth7Core.vhd:48
XauiGth7Core.xaui_tx_l1_p
out xaui_tx_l1_pstd_logic
Definition: XauiGth7Core.vhd:36
XauiGth7Core.xaui_tx_l3_p
out xaui_tx_l3_pstd_logic
Definition: XauiGth7Core.vhd:40
XauiGth7Core.xaui_rx_l2_n
in xaui_rx_l2_nstd_logic
Definition: XauiGth7Core.vhd:47
XauiGth7Core.debug
out debugstd_logic_vector( 5 downto 0)
Definition: XauiGth7Core.vhd:51
XauiGth7Core.configuration_vector
in configuration_vectorstd_logic_vector( 6 downto 0)
Definition: XauiGth7Core.vhd:52
XauiGth7Core.refclk
in refclkstd_logic
Definition: XauiGth7Core.vhd:29
XauiGth7Core.xaui_rx_l0_p
in xaui_rx_l0_pstd_logic
Definition: XauiGth7Core.vhd:42
XauiGth7Core.clk156_lock
out clk156_lockstd_logic
Definition: XauiGth7Core.vhd:28
XauiGth7Core.signal_detect
in signal_detectstd_logic_vector( 3 downto 0)
Definition: XauiGth7Core.vhd:50
XauiGth7Core.xaui_rx_l0_n
in xaui_rx_l0_nstd_logic
Definition: XauiGth7Core.vhd:43
XauiGth7Core.xaui_tx_l3_n
out xaui_tx_l3_nstd_logic
Definition: XauiGth7Core.vhd:41
XauiGth7Core.reset
in resetstd_logic
Definition: XauiGth7Core.vhd:26
XauiGth7Core.xaui_rx_l2_p
in xaui_rx_l2_pstd_logic
Definition: XauiGth7Core.vhd:46
XauiGth7Core.xaui_tx_l0_p
out xaui_tx_l0_pstd_logic
Definition: XauiGth7Core.vhd:34
XauiGth7Core.xaui_tx_l2_n
out xaui_tx_l2_nstd_logic
Definition: XauiGth7Core.vhd:39
XauiGth7Core.status_vector
out status_vectorstd_logic_vector( 7 downto 0)
Definition: XauiGth7Core.vhd:54
XauiGth7Core.xgmii_rxd
out xgmii_rxdstd_logic_vector( 63 downto 0)
Definition: XauiGth7Core.vhd:32
XauiGth7Core.xaui_rx_l1_p
in xaui_rx_l1_pstd_logic
Definition: XauiGth7Core.vhd:44
XauiGth7Core.xaui_rx_l1_n
in xaui_rx_l1_nstd_logic
Definition: XauiGth7Core.vhd:45
XauiGth7Core.xaui_tx_l2_p
out xaui_tx_l2_pstd_logic
Definition: XauiGth7Core.vhd:38
XauiGth7Core.xaui_tx_l1_n
out xaui_tx_l1_nstd_logic
Definition: XauiGth7Core.vhd:37
XauiGth7.ieee
_library_ ieeeieee
Definition: XauiGth7.vhd:18
XauiGth7Core.clk156_out
out clk156_outstd_logic
Definition: XauiGth7Core.vhd:27