SURF  1.0
Generics | Ports | Libraries | Use Clauses
TenGigEthGtx7Clk Entity Reference
ethernet » TenGigEthCore » gtx7
+ Inheritance diagram for TenGigEthGtx7Clk:
+ Collaboration diagram for TenGigEthGtx7Clk:

Entities

mapping  architecture
 

Libraries

ieee 
unisim 

Use Clauses

std_logic_1164 
StdRtlPkg  Package <StdRtlPkg>
vcomponents 

Generics

TPD_G  time := 1 ns
USE_GTREFCLK_G  boolean := false
REFCLK_DIV2_G  boolean := false
QPLL_REFCLK_SEL_G  bit_vector := " 001 "

Ports

extRst   in sl
phyClk   out sl
phyRst   out sl
gtRefClk   in sl := ' 0 '
gtClkP   in sl := ' 1 '
gtClkN   in sl := ' 0 '
gtClk   out sl
qplllock   out sl
qplloutclk   out sl
qplloutrefclk   out sl
qpllRst   in sl

Detailed Description

See also
entity

Definition at line 28 of file TenGigEthGtx7Clk.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 30 of file TenGigEthGtx7Clk.vhd.

◆ USE_GTREFCLK_G

USE_GTREFCLK_G boolean := false
Generic

Definition at line 31 of file TenGigEthGtx7Clk.vhd.

◆ REFCLK_DIV2_G

REFCLK_DIV2_G boolean := false
Generic

Definition at line 32 of file TenGigEthGtx7Clk.vhd.

◆ QPLL_REFCLK_SEL_G

QPLL_REFCLK_SEL_G bit_vector := " 001 "
Generic

Definition at line 33 of file TenGigEthGtx7Clk.vhd.

◆ extRst

extRst in sl
Port

Definition at line 36 of file TenGigEthGtx7Clk.vhd.

◆ phyClk

phyClk out sl
Port

Definition at line 37 of file TenGigEthGtx7Clk.vhd.

◆ phyRst

phyRst out sl
Port

Definition at line 38 of file TenGigEthGtx7Clk.vhd.

◆ gtRefClk

gtRefClk in sl := ' 0 '
Port

Definition at line 40 of file TenGigEthGtx7Clk.vhd.

◆ gtClkP

gtClkP in sl := ' 1 '
Port

Definition at line 41 of file TenGigEthGtx7Clk.vhd.

◆ gtClkN

gtClkN in sl := ' 0 '
Port

Definition at line 42 of file TenGigEthGtx7Clk.vhd.

◆ gtClk

gtClk out sl
Port

Definition at line 43 of file TenGigEthGtx7Clk.vhd.

◆ qplllock

qplllock out sl
Port

Definition at line 45 of file TenGigEthGtx7Clk.vhd.

◆ qplloutclk

qplloutclk out sl
Port

Definition at line 46 of file TenGigEthGtx7Clk.vhd.

◆ qplloutrefclk

qplloutrefclk out sl
Port

Definition at line 47 of file TenGigEthGtx7Clk.vhd.

◆ qpllRst

qpllRst in sl
Port

Definition at line 48 of file TenGigEthGtx7Clk.vhd.

◆ ieee

ieee
Library

Definition at line 18 of file TenGigEthGtx7Clk.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 19 of file TenGigEthGtx7Clk.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 21 of file TenGigEthGtx7Clk.vhd.

◆ unisim

unisim
Library

Definition at line 23 of file TenGigEthGtx7Clk.vhd.

◆ vcomponents

vcomponents
Package

Definition at line 24 of file TenGigEthGtx7Clk.vhd.

The documentation for this class was generated from the following file: