SURF  1.0
Generics | Ports | Libraries | Use Clauses
AxiStreamMux Entity Reference
axi
+ Inheritance diagram for AxiStreamMux:
+ Collaboration diagram for AxiStreamMux:

Entities

structure  architecture
 

Libraries

ieee 

Use Clauses

std_logic_1164 
std_logic_arith 
std_logic_unsigned 
StdRtlPkg  Package <StdRtlPkg>
ArbiterPkg  Package <ArbiterPkg>
AxiStreamPkg  Package <AxiStreamPkg>

Generics

TPD_G  time := 1 ns
NUM_SLAVES_G  integer range 1 to 32 := 4
MODE_G  string := " INDEXED "
TDEST_ROUTES_G  Slv8Array := ( 0 = > " -------- " )
PIPE_STAGES_G  integer range 0 to 16 := 0
TDEST_LOW_G  integer range 0 to 7 := 0
ILEAVE_EN_G  boolean := false
ILEAVE_REARB_G  natural := 0

Ports

axisClk   in sl
axisRst   in sl
sAxisMasters   in AxiStreamMasterArray ( NUM_SLAVES_G - 1 downto 0 )
sAxisSlaves   out AxiStreamSlaveArray ( NUM_SLAVES_G - 1 downto 0 )
disableSel   in slv ( NUM_SLAVES_G - 1 downto 0 ) := ( others = > ' 0 ' )
mAxisMaster   out AxiStreamMasterType
mAxisSlave   in AxiStreamSlaveType

Detailed Description

See also
entity

Definition at line 31 of file AxiStreamMux.vhd.

Member Data Documentation

◆ TPD_G

TPD_G time := 1 ns
Generic

Definition at line 33 of file AxiStreamMux.vhd.

◆ NUM_SLAVES_G

NUM_SLAVES_G integer range 1 to 32 := 4
Generic

Definition at line 34 of file AxiStreamMux.vhd.

◆ MODE_G

MODE_G string := " INDEXED "
Generic

Definition at line 35 of file AxiStreamMux.vhd.

◆ TDEST_ROUTES_G

TDEST_ROUTES_G Slv8Array := ( 0 = > " -------- " )
Generic

Definition at line 36 of file AxiStreamMux.vhd.

◆ PIPE_STAGES_G

PIPE_STAGES_G integer range 0 to 16 := 0
Generic

Definition at line 37 of file AxiStreamMux.vhd.

◆ TDEST_LOW_G

TDEST_LOW_G integer range 0 to 7 := 0
Generic

Definition at line 38 of file AxiStreamMux.vhd.

◆ ILEAVE_EN_G

ILEAVE_EN_G boolean := false
Generic

Definition at line 39 of file AxiStreamMux.vhd.

◆ ILEAVE_REARB_G

ILEAVE_REARB_G natural := 0
Generic

Definition at line 40 of file AxiStreamMux.vhd.

◆ axisClk

axisClk in sl
Port

Definition at line 43 of file AxiStreamMux.vhd.

◆ axisRst

axisRst in sl
Port

Definition at line 44 of file AxiStreamMux.vhd.

◆ sAxisMasters

sAxisMasters in AxiStreamMasterArray ( NUM_SLAVES_G - 1 downto 0 )
Port

Definition at line 46 of file AxiStreamMux.vhd.

◆ sAxisSlaves

sAxisSlaves out AxiStreamSlaveArray ( NUM_SLAVES_G - 1 downto 0 )
Port

Definition at line 47 of file AxiStreamMux.vhd.

◆ disableSel

disableSel in slv ( NUM_SLAVES_G - 1 downto 0 ) := ( others = > ' 0 ' )
Port

Definition at line 48 of file AxiStreamMux.vhd.

◆ mAxisMaster

mAxisMaster out AxiStreamMasterType
Port

Definition at line 50 of file AxiStreamMux.vhd.

◆ mAxisSlave

mAxisSlave in AxiStreamSlaveType
Port

Definition at line 51 of file AxiStreamMux.vhd.

◆ ieee

ieee
Library

Definition at line 20 of file AxiStreamMux.vhd.

◆ std_logic_1164

std_logic_1164
Package

Definition at line 21 of file AxiStreamMux.vhd.

◆ std_logic_arith

std_logic_arith
Package

Definition at line 22 of file AxiStreamMux.vhd.

◆ std_logic_unsigned

std_logic_unsigned
Package

Definition at line 23 of file AxiStreamMux.vhd.

◆ StdRtlPkg

StdRtlPkg
Package

Definition at line 25 of file AxiStreamMux.vhd.

◆ ArbiterPkg

ArbiterPkg
Package

Definition at line 26 of file AxiStreamMux.vhd.

◆ AxiStreamPkg

AxiStreamPkg
Package

Definition at line 27 of file AxiStreamMux.vhd.

The documentation for this class was generated from the following file: