SURF  1.0
SynchronizerOneShotVector.vhd
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1 -------------------------------------------------------------------------------
2 -- File : SynchronizerOneShotVector.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2014-04-11
5 -- Last update: 2016-11-04
6 -------------------------------------------------------------------------------
7 -- Description: Wrapper for multiple SynchronizerOneShot modules
8 -------------------------------------------------------------------------------
9 -- This file is part of 'SLAC Firmware Standard Library'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'SLAC Firmware Standard Library', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 
21 use work.StdRtlPkg.all;
22 
23 --! @see entity
24  --! @ingroup base_sync
26  generic (
27  TPD_G : time := 1 ns; -- Simulation FF output delay
28  RST_POLARITY_G : sl := '1'; -- '1' for active HIGH reset, '0' for active LOW reset
29  RST_ASYNC_G : boolean := false; -- Reset is asynchronous
30  BYPASS_SYNC_G : boolean := false; -- Bypass RstSync module for synchronous data configuration
31  RELEASE_DELAY_G : positive := 3; -- Delay between deassertion of async and sync resets
32  IN_POLARITY_G : slv := "1"; -- 0 for active LOW, 1 for active HIGH
33  OUT_POLARITY_G : slv := "1"; -- 0 for active LOW, 1 for active HIGH
34  PULSE_WIDTH_G : positive := 1; -- one-shot pulse width duration (units of clk cycles)
35  WIDTH_G : positive := 16);
36  port (
37  clk : in sl; -- Clock to be SYNC'd to
38  rst : in sl := not RST_POLARITY_G; -- Optional reset
39  dataIn : in slv(WIDTH_G-1 downto 0); -- Data to be 'synced'
40  dataOut : out slv(WIDTH_G-1 downto 0)); -- synced data
41 end SynchronizerOneShotVector;
42 
43 architecture mapping of SynchronizerOneShotVector is
44 
45  type PolarityVectorArray is array (WIDTH_G-1 downto 0) of sl;
46 
47  function FillVectorArray (INPUT : slv)
48  return PolarityVectorArray is
49  variable retVar : PolarityVectorArray := (others => '1');
50  begin
51  if INPUT = "1" then
52  retVar := (others => '1');
53  else
54  for i in WIDTH_G-1 downto 0 loop
55  retVar(i) := INPUT(i);
56  end loop;
57  end if;
58  return retVar;
59  end function FillVectorArray;
60 
61  constant IN_POLARITY_C : PolarityVectorArray := FillVectorArray(IN_POLARITY_G);
62  constant OUT_POLARITY_C : PolarityVectorArray := FillVectorArray(OUT_POLARITY_G);
63 
64 begin
65 
66  GEN_VEC :
67  for i in (WIDTH_G-1) downto 0 generate
68 
69  SyncOneShot_Inst : entity work.SynchronizerOneShot
70  generic map (
71  TPD_G => TPD_G,
79  port map (
80  clk => clk,
81  rst => rst,
82  dataIn => dataIn(i),
83  dataOut => dataOut(i));
84 
85  end generate GEN_VEC;
86 
87 end architecture mapping;
PolarityVectorArray := FillVectorArray(IN_POLARITY_G ) IN_POLARITY_C
out dataOutslv( WIDTH_G- 1 downto 0)
std_logic sl
Definition: StdRtlPkg.vhd:28
in rstsl :=not RST_POLARITY_G
RST_ASYNC_Gboolean := false
in rstsl :=not RST_POLARITY_G
BYPASS_SYNC_Gboolean := false
( WIDTH_G- 1 downto 0) sl PolarityVectorArray
in dataInslv( WIDTH_G- 1 downto 0)
PolarityVectorArray := FillVectorArray(OUT_POLARITY_G ) OUT_POLARITY_C
std_logic_vector slv
Definition: StdRtlPkg.vhd:29