1 ------------------------------------------------------------------------------- 2 -- File : Gtx7RxFixedLatPhaseAligner.vhd 3 -- Company : SLAC National Accelerator Laboratory 4 -- Created : 2012-11-06 5 -- Last update: 2014-01-30 6 ------------------------------------------------------------------------------- 8 -- Used in conjunction for a Xilinx 7 Series GTX. 9 -- Given raw 8b10b encoded data presented 2 bytes at a time (20 bits), 10 -- attempts to align any observed comma to the lower byte. 11 -- Assumes GTX comma align is enabled and in PMA mode. 12 -- Comma is configurable through the COMMA_G generic. 13 -- If an odd number of rxSlides is required for alignment, resets the GTX RX 14 -- so that a new CDR lock can be obtained. The GTX in PMA Slide Mode shifts 15 -- the phase of the output clock only every other slide. This module's 16 -- purpose is to obtain an output clock that exactly matches the phase of the 18 ------------------------------------------------------------------------------- 19 -- This file is part of 'SLAC Firmware Standard Library'. 20 -- It is subject to the license terms in the LICENSE.txt file found in the 21 -- top-level directory of this distribution and at: 22 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. 23 -- No part of 'SLAC Firmware Standard Library', including this file, 24 -- may be copied, modified, propagated, or distributed except according to 25 -- the terms contained in the LICENSE.txt file. 26 ------------------------------------------------------------------------------- 29 use ieee.std_logic_1164.
all;
30 use ieee.numeric_std.
all;
35 --! @ingroup xilinx_7Series_gtx7 54 end entity Gtx7RxFixedLatPhaseAligner;
58 constant SLIDE_WAIT_C : := 32;
-- Dictated by UG476 GTX Tranceiver Guide 60 type StateType is (SEARCH_S, RESET_S, SLIDE_S, SLIDE_WAIT_S, ALIGNED_S);
62 type RegType is record 67 slideWaitCounter : (bitSize(SLIDE_WAIT_C)-1 downto 0);
74 constant REG_RESET_C : RegType := 77 last => (others => '0'), 78 slideCount => (others => '0'), 79 slideWaitCounter => (others => '0'), 84 signal r, rin : RegType := REG_RESET_C;
86 signal rxRunPhAlignmentSync : sl;
88 attribute dont_touch : ;
89 attribute dont_touch of r : signal is "TRUE";
91 attribute KEEP_HIERARCHY : ;
92 attribute KEEP_HIERARCHY of 93 RstSync_1 : label is "TRUE";
97 -- Must use async resets since rxUsrClk can drop out 106 syncRst => rxRunPhAlignmentSync
);
109 comb :
process (r,
rxData)
is 110 variable v : RegType;
122 -- Look for pos or neg comma 128 -- Latch the Alignment Value 129 v.alignmentValue := i;
131 v.state := ALIGNED_S;
132 elsif (i mod 2 = 0) then 133 -- Latch the Alignment Value 134 v.alignmentValue := i;
135 -- Even number of slides needed 136 -- slideCount set to number of slides needed - 1 137 v.slideCount := to_unsigned(i-1, bitSize(WORD_SIZE_G));
140 -- Latch the Alignment Value 141 v.alignmentValue := i;
142 -- Reset the rx and hope for a new lock requiring an even number of slides 149 -- Async reset will eventually get everything back to SEARCH_S state 154 v.state := SLIDE_WAIT_S;
157 -- Wait SLIDE_WAIT_C clocks between each slide 158 v.slideWaitCounter := r.slideWaitCounter + 1;
159 if (uAnd(slv(r.slideWaitCounter)) = '1') then 160 if (r.slideCount = 0) then 161 v.state := SEARCH_S;
-- Double check that the slides worked 163 v.slideCount := r.slideCount - 1;
170 -- Gtx7RxRst module will reset this module back to SEARCH_S if alignment is lost 182 seq :
process (rxRunPhAlignmentSync,
rxUsrClk)
is 185 r <= rin after TPD_G;
187 if (rxRunPhAlignmentSync = '0') then 188 r <= REG_RESET_C after TPD_G;
192 end architecture rtl;
out rxPhaseAlignmentDonesl
COMMA_EN_Gslv( 3 downto 0) := "0011"
COMMA_3_Gslv := "XXXXXXXXXXXXXXXXXXXX"
in rxDataslv( WORD_SIZE_G- 1 downto 0)
COMMA_2_Gslv := "XXXXXXXXXXXXXXXXXXXX"
COMMA_1_Gslv := "----------1010000011"
COMMA_0_Gslv := "----------0101111100"