SURF  1.0
Gtp7RxFixedLatPhaseAligner.vhd
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1 -------------------------------------------------------------------------------
2 -- File : Gtp7RxFixedLatPhaseAligner.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2012-11-06
5 -- Last update: 2016-12-16
6 -------------------------------------------------------------------------------
7 -- Description:
8 -- Used in conjunction for a Xilinx 7 Series GTX.
9 -- Given raw 8b10b encoded data presented 2 bytes at a time (20 bits),
10 -- attempts to align any observed comma to the lower byte.
11 -- Assumes GTX comma align is enabled and in PMA mode.
12 -- Comma is configurable through the COMMA_G generic.
13 -- If an odd number of rxSlides is required for alignment, resets the GTX RX
14 -- so that a new CDR lock can be obtained. The GTX in PMA Slide Mode shifts
15 -- the phase of the output clock only every other slide. This module's
16 -- purpose is to obtain an output clock that exactly matches the phase of the
17 -- commas.
18 -------------------------------------------------------------------------------
19 -- This file is part of 'SLAC Firmware Standard Library'.
20 -- It is subject to the license terms in the LICENSE.txt file found in the
21 -- top-level directory of this distribution and at:
22 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
23 -- No part of 'SLAC Firmware Standard Library', including this file,
24 -- may be copied, modified, propagated, or distributed except according to
25 -- the terms contained in the LICENSE.txt file.
26 -------------------------------------------------------------------------------
27 
28 library ieee;
29 use ieee.std_logic_1164.all;
30 use ieee.numeric_std.all;
31 
32 use work.StdRtlPkg.all;
33 
34 --! @see entity
35  --! @ingroup xilinx_7Series_gtp7
37 
38  generic (
39  TPD_G : time := 1 ns;
40  WORD_SIZE_G : integer := 20;
41  COMMA_EN_G : slv(3 downto 0) := "0011";
42  COMMA_0_G : slv := "----------0101111100";
43  COMMA_1_G : slv := "----------1010000011";
44  COMMA_2_G : slv := "XXXXXXXXXXXXXXXXXXXX";
45  COMMA_3_G : slv := "XXXXXXXXXXXXXXXXXXXX");
46  port (
47  rxUsrClk : in sl;
48  rxRunPhAlignment : in sl; -- From RxRst, active low reset, not clocked by rxUsrClk
49  rxData : in slv(WORD_SIZE_G-1 downto 0); -- Encoded raw rx data
50  rxReset : out sl;
51  rxSlide : out sl; -- RXSLIDE input to GTX
52  rxPhaseAlignmentDone : out sl); -- Alignment has been achieved.
53 
54 end entity Gtp7RxFixedLatPhaseAligner;
55 
56 architecture rtl of Gtp7RxFixedLatPhaseAligner is
57 
58  constant SLIDE_WAIT_C : integer := 64; -- Dictated by UG476 GTX Tranceiver Guide
59 
60  type StateType is (SEARCH_S, RESET_S, SLIDE_S, SLIDE_WAIT_S, ALIGNED_S);
61 
62  type RegType is record
63  state : StateType;
64  last : slv(WORD_SIZE_G*2-1 downto 0);
65  slideCount : unsigned(bitSize(WORD_SIZE_G)-1 downto 0);
66  slideWaitCounter : unsigned(bitSize(SLIDE_WAIT_C)-1 downto 0);
67  rxReset : sl;
68  rxSlide : sl; -- Output
69  rxPhaseAlignmentDone : sl; --Output
70  end record RegType;
71 
72  constant REG_RESET_C : RegType :=
73  (state => SEARCH_S,
74  last => (others => '0'),
75  slideCount => (others => '0'),
76  slideWaitCounter => (others => '0'),
77  rxReset => '0',
78  rxSlide => '0',
79  rxPhaseAlignmentDone => '0');
80 
81  signal r, rin : RegType := REG_RESET_C;
82 
83  signal rxRunPhAlignmentSync : sl;
84 
85 begin
86 
87  -- Must use async resets since rxUsrClk can drop out
88  RstSync_1 : entity work.RstSync
89  generic map (
90  TPD_G => TPD_G,
91  IN_POLARITY_G => '0',
92  OUT_POLARITY_G => '0')
93  port map (
94  clk => rxUsrClk,
96  syncRst => rxRunPhAlignmentSync);
97 
98 
99  comb : process (r, rxData) is
100  variable v : RegType;
101  begin
102  v := r;
103 
104  v.rxSlide := '0';
105  v.rxPhaseAlignmentDone := '0';
106 
107  v.last := rxData & r.last(WORD_SIZE_G*2-1 downto WORD_SIZE_G); -- Save last word
108 
109  case r.state is
110  when SEARCH_S =>
111  for i in 0 to WORD_SIZE_G - 1 loop
112  -- Look for pos or neg comma
113  if (std_match(r.last((i+WORD_SIZE_G-1) downto i), COMMA_0_G) and (COMMA_EN_G(0) = '1')) or
114  (std_match(r.last((i+WORD_SIZE_G-1) downto i), COMMA_1_G) and (COMMA_EN_G(1) = '1')) or
115  (std_match(r.last((i+WORD_SIZE_G-1) downto i), COMMA_2_G) and (COMMA_EN_G(2) = '1')) or
116  (std_match(r.last((i+WORD_SIZE_G-1) downto i), COMMA_3_G) and (COMMA_EN_G(3) = '1')) then
117  if (i = 0) then
118  v.state := ALIGNED_S;
119  elsif (i mod 2 = 0) then
120  -- Even number of slides needed
121  -- slideCount set to number of slides needed - 1
122  v.slideCount := to_unsigned(i-1, bitSize(WORD_SIZE_G));
123  v.state := SLIDE_S;
124  else
125  -- Reset the rx and hope for a new lock requiring an even number of slides
126  v.state := RESET_S;
127  end if;
128  end if;
129  end loop;
130 
131  when RESET_S =>
132  -- Async reset will eventually get everything back to SEARCH_S state
133  v.rxReset := '1';
134 
135  when SLIDE_S =>
136  v.rxSlide := '1';
137  v.state := SLIDE_WAIT_S;
138 
139  when SLIDE_WAIT_S =>
140  -- Wait SLIDE_WAIT_C clocks between each slide
141  v.slideWaitCounter := r.slideWaitCounter + 1;
142  if (uAnd(slv(r.slideWaitCounter)) = '1') then
143  if (r.slideCount = 0) then
144  v.state := SEARCH_S; -- Double check that the slides worked
145  else
146  v.slideCount := r.slideCount - 1;
147  v.state := SLIDE_S;
148  end if;
149  end if;
150 
151  when ALIGNED_S =>
152  v.rxPhaseAlignmentDone := '1';
153  -- Gtx7RxRst module will reset this module back to SEARCH_S if alignment is lost
154 
155  end case;
156 
157  rin <= v;
158 
159  -- Outputs
160  rxReset <= r.rxReset;
161  rxSlide <= r.rxSlide;
163  end process comb;
164 
165  seq : process (rxRunPhAlignmentSync, rxUsrClk) is
166  begin
167  if (rising_edge(rxUsrClk)) then
168  r <= rin after TPD_G;
169  end if;
170  if (rxRunPhAlignmentSync = '0') then
171  r <= REG_RESET_C after TPD_G;
172  end if;
173  end process;
174 
175 end architecture rtl;
out syncRstsl
Definition: RstSync.vhd:36
IN_POLARITY_Gsl := '1'
Definition: RstSync.vhd:28
std_logic sl
Definition: StdRtlPkg.vhd:28
in rxDataslv( WORD_SIZE_G- 1 downto 0)
in asyncRstsl
Definition: RstSync.vhd:35
in clksl
Definition: RstSync.vhd:34
OUT_POLARITY_Gsl := '1'
Definition: RstSync.vhd:29
COMMA_1_Gslv := "----------1010000011"
COMMA_EN_Gslv( 3 downto 0) := "0011"
COMMA_3_Gslv := "XXXXXXXXXXXXXXXXXXXX"
COMMA_0_Gslv := "----------0101111100"
TPD_Gtime := 1 ns
Definition: RstSync.vhd:27
COMMA_2_Gslv := "XXXXXXXXXXXXXXXXXXXX"
std_logic_vector slv
Definition: StdRtlPkg.vhd:29