SURF  1.0
EthMacTxShift.vhd
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1 -------------------------------------------------------------------------------
2 -- File : EthMacTxShift.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2016-09-08
5 -- Last update: 2016-09-14
6 -------------------------------------------------------------------------------
7 -- Description: Ethernet MAC's TX byte Shifting Module
8 -------------------------------------------------------------------------------
9 -- This file is part of 'SLAC Firmware Standard Library'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'SLAC Firmware Standard Library', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 use ieee.std_logic_arith.all;
21 use ieee.std_logic_unsigned.all;
22 
23 use work.AxiStreamPkg.all;
24 use work.StdRtlPkg.all;
25 use work.EthMacPkg.all;
26 
27 --! @see entity
28  --! @ingroup ethernet_EthMacCore
29 entity EthMacTxShift is
30  generic (
31  TPD_G : time := 1 ns;
32  SHIFT_EN_G : boolean := false);
33  port (
34  -- Clock and Reset
35  ethClk : in sl;
36  ethRst : in sl;
37  -- AXIS Interface
42  -- Configuration
43  txShift : in slv(3 downto 0));
44 end EthMacTxShift;
45 
46 architecture mapping of EthMacTxShift is
47 
48 begin
49 
50  U_TxShiftEnGen : if (SHIFT_EN_G = true) generate
51  -- Shift outbound data n bytes to the right.
52  -- This removes bytes of data at start
53  -- of the packet. These were added by software
54  -- to create a software friendly alignment of
55  -- outbound data.
56  U_TxShift : entity work.AxiStreamShift
57  generic map (
58  TPD_G => TPD_G,
60  port map (
61  axisClk => ethClk,
62  axisRst => ethRst,
63  axiStart => '1',
64  axiShiftDir => '1', -- 1 = right (msb to lsb)
70  end generate;
71 
72  U_TxShiftDisGen : if (SHIFT_EN_G = false) generate
75  end generate;
76 
77 end mapping;
SHIFT_EN_Gboolean := false
out sAxisSlaveAxiStreamSlaveType
std_logic sl
Definition: StdRtlPkg.vhd:28
in mAxisSlaveAxiStreamSlaveType
out sAxisSlaveAxiStreamSlaveType
in sAxisMasterAxiStreamMasterType
in txShiftslv( 3 downto 0)
in axiShiftCntslv( 3 downto 0)
TPD_Gtime := 1 ns
TPD_Gtime := 1 ns
out mAxisMasterAxiStreamMasterType
in sAxisMasterAxiStreamMasterType
out mAxisMasterAxiStreamMasterType
_library_ ieeeieee
in mAxisSlaveAxiStreamSlaveType
AXIS_CONFIG_GAxiStreamConfigType := AXI_STREAM_CONFIG_INIT_C
AxiStreamConfigType :=(TSTRB_EN_C => false,TDATA_BYTES_C => 16,TDEST_BITS_C => 8,TID_BITS_C => 0,TKEEP_MODE_C => TKEEP_COMP_C,TUSER_BITS_C => 4,TUSER_MODE_C => TUSER_FIRST_LAST_C) EMAC_AXIS_CONFIG_C
Definition: EthMacPkg.vhd:58
std_logic_vector slv
Definition: StdRtlPkg.vhd:29