SURF  1.0
EthMacRxImport.vhd
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1 -------------------------------------------------------------------------------
2 -- File : EthMacRxImport.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2016-09-09
5 -- Last update: 2016-09-14
6 -------------------------------------------------------------------------------
7 -- Description: Mapping for 1GbE/10GbE/40GbE ETH MAC RX path
8 -------------------------------------------------------------------------------
9 -- This file is part of 'SLAC Firmware Standard Library'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'SLAC Firmware Standard Library', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 use ieee.std_logic_arith.all;
21 use ieee.std_logic_unsigned.all;
22 
23 use work.AxiStreamPkg.all;
24 use work.StdRtlPkg.all;
25 use work.EthMacPkg.all;
26 
27 --! @see entity
28  --! @ingroup ethernet_EthMacCore
29 entity EthMacRxImport is
30  generic (
31  TPD_G : time := 1 ns;
32  PHY_TYPE_G : string := "XGMII");
33  port (
34  -- Clock and Reset
35  ethClk : in sl;
36  ethRst : in sl;
37  -- AXIS Interface
39  -- XLGMII PHY Interface
40  xlgmiiRxd : in slv(127 downto 0);
41  xlgmiiRxc : in slv(15 downto 0);
42  -- XGMII PHY Interface
43  xgmiiRxd : in slv(63 downto 0);
44  xgmiiRxc : in slv(7 downto 0);
45  -- GMII PHY Interface
46  gmiiRxDv : in sl;
47  gmiiRxEr : in sl;
48  gmiiRxd : in slv(7 downto 0);
49  -- Configuration and status
50  phyReady : in sl;
51  rxCountEn : out sl;
52  rxCrcError : out sl);
53 end EthMacRxImport;
54 
55 architecture mapping of EthMacRxImport is
56 
57 begin
58 
59  assert ((PHY_TYPE_G = "XLGMII") or (PHY_TYPE_G = "XGMII") or (PHY_TYPE_G = "GMII")) report "EthMacRxImport: PHY_TYPE_G must be either GMII, XGMII, XLGMII" severity failure;
60 
61  U_40G : if (PHY_TYPE_G = "XLGMII") generate
62  U_XLGMII : entity work.EthMacRxImportXlgmii
63  generic map (
64  TPD_G => TPD_G)
65  port map (
66  -- Clock and Reset
67  ethClk => ethClk,
68  ethRst => ethRst,
69  -- AXIS Interface
71  -- XLGMII PHY Interface
72  phyRxd => xlgmiiRxd,
73  phyRxc => xlgmiiRxc,
74  -- Configuration and status
75  phyReady => phyReady,
78  end generate;
79 
80  U_10G : if (PHY_TYPE_G = "XGMII") generate
81  U_XGMII : entity work.EthMacRxImportXgmii
82  generic map (
83  TPD_G => TPD_G)
84  port map (
85  -- Clock and Reset
86  ethClk => ethClk,
87  ethRst => ethRst,
88  -- AXIS Interface
90  -- XGMII PHY Interface
91  phyRxd => xgmiiRxd,
92  phyRxc => xgmiiRxc,
93  -- Configuration and status
94  phyReady => phyReady,
97  end generate;
98 
99  U_1G : if (PHY_TYPE_G = "GMII") generate
100  U_GMII : entity work.EthMacRxImportGmii
101  generic map (
102  TPD_G => TPD_G)
103  port map (
104  -- Clock and Reset
105  ethClk => ethClk,
106  ethRst => ethRst,
107  -- AXIS Interface
109  -- GMII PHY Interface
110  gmiiRxDv => gmiiRxDv,
111  gmiiRxEr => gmiiRxEr,
112  gmiiRxd => gmiiRxd,
113  -- Configuration and status
114  phyReady => phyReady,
115  rxCountEn => rxCountEn,
117  end generate;
118 
119 end mapping;
out macIbMasterAxiStreamMasterType
in xgmiiRxdslv( 63 downto 0)
in xlgmiiRxcslv( 15 downto 0)
std_logic sl
Definition: StdRtlPkg.vhd:28
in xgmiiRxcslv( 7 downto 0)
PHY_TYPE_Gstring := "XGMII"
in phyRxdslv( 63 downto 0)
in xlgmiiRxdslv( 127 downto 0)
in phyRxcslv( 15 downto 0)
_library_ ieeeieee
in phyRxcslv( 7 downto 0)
in gmiiRxdslv( 7 downto 0)
in phyRxdslv( 127 downto 0)
out macIbMasterAxiStreamMasterType
in gmiiRxdslv( 7 downto 0)
out macIbMasterAxiStreamMasterType
out macIbMasterAxiStreamMasterType
TPD_Gtime := 1 ns
std_logic_vector slv
Definition: StdRtlPkg.vhd:29