SURF  1.0
DspCounter.vhd
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1 -------------------------------------------------------------------------------
2 -- File : DspCounter.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2013-07-12
5 -- Last update: 2013-08-02
6 -------------------------------------------------------------------------------
7 -- Description: Example of Counter that infers a DSP48 via "use_dsp48" attribute
8 -------------------------------------------------------------------------------
9 -- This file is part of 'SLAC Firmware Standard Library'.
10 -- It is subject to the license terms in the LICENSE.txt file found in the
11 -- top-level directory of this distribution and at:
12 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
13 -- No part of 'SLAC Firmware Standard Library', including this file,
14 -- may be copied, modified, propagated, or distributed except according to
15 -- the terms contained in the LICENSE.txt file.
16 -------------------------------------------------------------------------------
17 
18 library ieee;
19 use ieee.std_logic_1164.all;
20 use ieee.std_logic_unsigned.all;
21 use ieee.std_logic_arith.all;
22 
23 use work.StdRtlPkg.all;
24 
25 --! @see entity
26  --! @ingroup base_general
27 entity DspCounter is
28  generic (
29  TPD_G : time := 1 ns;
30  RST_POLARITY_G : sl := '1'; -- '1' for active high rst, '0' for active low
31  RST_ASYNC_G : boolean := false;
32  DATA_WIDTH_G : integer range 1 to 48 := 16;
33  INCREMENT_G : integer range 1 to 48 := 1);
34  port (
35  clk : in sl := '0';
36  rst : in sl := '0';
37  en : in sl := '1';
38  cnt : out slv(DATA_WIDTH_G-1 downto 0));
39 end DspCounter;
40 
41 architecture rtl of DspCounter is
42  -- Constants
43  constant INCREMENT_C : slv(DATA_WIDTH_G-1 downto 0) := conv_std_logic_vector(INCREMENT_G, DATA_WIDTH_G);
44 
45  -- Signals
46  signal counter : slv(DATA_WIDTH_G-1 downto 0) := (others => '0');
47 
48  -- Attribute for XST
49  attribute use_dsp48 : string;
50  attribute use_dsp48 of counter : signal is "yes";
51 
52 begin
53 
54  -- INCREMENT_G range check
55  assert (INCREMENT_G <= ((2**DATA_WIDTH_G)-1))
56  report "INCREMENT_G must be <= ((2**DATA_WIDTH_G)-1)"
57  severity failure;
58 
59  cnt <= counter;
60 
61  process(clk, rst)
62  begin
63  --asychronous reset
64  if (RST_ASYNC_G and rst = RST_POLARITY_G) then
65  counter <= (others => '0') after TPD_G;
66  elsif rising_edge(clk) then
67  --sychronous reset
68  if (RST_ASYNC_G = false and rst = RST_POLARITY_G) then
69  counter <= (others => '0') after TPD_G;
70  else
71  if en = '1' then
72  counter <= counter + INCREMENT_C after TPD_G;
73  end if;
74  end if;
75  end if;
76  end process;
77 
78 end rtl;
RST_ASYNC_Gboolean := false
Definition: DspCounter.vhd:31
_library_ ieeeieee
Definition: DS2411Core.vhd:18
std_logic sl
Definition: StdRtlPkg.vhd:28
DATA_WIDTH_Ginteger range 1 to 48:= 16
Definition: DspCounter.vhd:32
TPD_Gtime := 1 ns
Definition: DspCounter.vhd:29
in rstsl := '0'
Definition: DspCounter.vhd:36
RST_POLARITY_Gsl := '1'
Definition: DspCounter.vhd:30
in clksl := '0'
Definition: DspCounter.vhd:35
INCREMENT_Ginteger range 1 to 48:= 1
Definition: DspCounter.vhd:33
in ensl := '1'
Definition: DspCounter.vhd:37
out cntslv( DATA_WIDTH_G- 1 downto 0)
Definition: DspCounter.vhd:38
std_logic_vector slv
Definition: StdRtlPkg.vhd:29