SURF  1.0
AxiDmaPkg.vhd
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1 -------------------------------------------------------------------------------
2 -- File : AxiStreamDmaRead.vhd
3 -- Company : SLAC National Accelerator Laboratory
4 -- Created : 2013-05-06
5 -- Standard : VHDL'93/02
6 -------------------------------------------------------------------------------
7 -- Description:
8 -- Package file for AXI DMA Controller
9 -------------------------------------------------------------------------------
10 -- This file is part of 'SLAC Firmware Standard Library'.
11 -- It is subject to the license terms in the LICENSE.txt file found in the
12 -- top-level directory of this distribution and at:
13 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html.
14 -- No part of 'SLAC Firmware Standard Library', including this file,
15 -- may be copied, modified, propagated, or distributed except according to
16 -- the terms contained in the LICENSE.txt file.
17 -------------------------------------------------------------------------------
18 
19 library ieee;
20 use ieee.std_logic_1164.all;
21 
22 use work.StdRtlPkg.all;
23 use work.AxiStreamPkg.all;
24 
25 package AxiDmaPkg is
26 --! @file
27  --! @ingroup axi
28 
29  -------------------------------------
30  -- Write DMA Axi-Stream Configuration
31  -------------------------------------
33  TSTRB_EN_C => false,
34  TDATA_BYTES_C => 8,
35  TDEST_BITS_C => 8,
36  TID_BITS_C => 0,
37  TKEEP_MODE_C => TKEEP_COMP_C,
38  TUSER_BITS_C => 8,
39  TUSER_MODE_C => TUSER_FIRST_LAST_C);
40 
41  -------------------------------------
42  -- Write DMA Request (AxiStreamDmaWrite)
43  -------------------------------------
44 
45  -- Base Record
46  type AxiWriteDmaReqType is record
48  drop : sl;
49  address : slv(63 downto 0);
50  maxSize : slv(31 downto 0);
51  end record;
52 
53  -- Initialization constants
55  request => '0',
56  drop => '0',
57  address => (others=>'0'),
58  maxSize => (others=>'0')
59  );
60 
61  -- Array
62  type AxiWriteDmaReqArray is array (natural range<>) of AxiWriteDmaReqType;
63 
64  -------------------------------------
65  -- Write DMA Acknowledge (AxiStreamDmaWrite)
66  -------------------------------------
67 
68  -- Base Record
69  type AxiWriteDmaAckType is record
70  idle : sl;
71  done : sl;
72  size : slv(31 downto 0);
75  errorValue : slv(1 downto 0);
76  firstUser : slv(7 downto 0);
77  lastUser : slv(7 downto 0);
78  dest : slv(7 downto 0);
79  id : slv(7 downto 0);
80  end record;
81 
82  -- Initialization constants
84  idle => '1',
85  done => '0',
86  size => (others=>'0'),
87  overflow => '0',
88  writeError => '0',
89  errorValue => "00",
90  firstUser => (others=>'0'),
91  lastUser => (others=>'0'),
92  dest => (others=>'0'),
93  id => (others=>'0')
94  );
95 
96  -- Array
97  type AxiWriteDmaAckArray is array (natural range<>) of AxiWriteDmaAckType;
98 
99  -------------------------------------
100  -- Read DMA Request (AxiStreamDmaRead)
101  -------------------------------------
102 
103  -- Base Record
104  type AxiReadDmaReqType is record
105  request : sl;
106  address : slv(63 downto 0);
107  size : slv(31 downto 0);
108  firstUser : slv(7 downto 0);
109  lastUser : slv(7 downto 0);
110  dest : slv(7 downto 0);
111  id : slv(7 downto 0);
112  end record;
113 
114  -- Initialization constants
116  request => '0',
117  address => (others=>'0'),
118  size => (others=>'0'),
119  firstUser => (others=>'0'),
120  lastUser => (others=>'0'),
121  dest => (others=>'0'),
122  id => (others=>'0')
123  );
124 
125  -- Array
126  type AxiReadDmaReqArray is array (natural range<>) of AxiReadDmaReqType;
127 
128  -------------------------------------
129  -- Read DMA Acknowledge (AxiStreamDmaRead)
130  -------------------------------------
131 
132  -- Base Record
133  type AxiReadDmaAckType is record
134  idle : sl;
135  done : sl;
137  errorValue : slv(1 downto 0);
138  end record;
139 
140  -- Initialization constants
142  idle => '1',
143  done => '0',
144  readError => '0',
145  errorValue => "00"
146  );
147 
148  -- Array
149  type AxiReadDmaAckArray is array (natural range<>) of AxiReadDmaAckType;
150 
151 
152  -------------------------------------
153  -- DMA Write Descriptor Request (AxiStreamDmaV2)
154  -- Issued from dma write engine to request a free
155  -- descriptor from the pool.
156  -------------------------------------
157 
158  type AxiWriteDmaDescReqType is record
160  dest : slv(7 downto 0);
161  end record;
162 
164  valid => '0',
165  dest => (others=>'0')
166  );
167 
168  type AxiWriteDmaDescReqArray is array (natural range<>) of AxiWriteDmaDescReqType;
169 
170  constant AXI_WRITE_DMA_DESC_REQ_SIZE_C : integer := 8;
171 
172  function toSlv (r : AxiWriteDmaDescReqType ) return slv;
174 
175 
176  -------------------------------------
177  -- DMA Write Descriptor Ack (AxiStreamDmaV2)
178  -- Returned to dma write engine in response to
179  -- AxiWriteDescReqType.
180  -------------------------------------
181 
182  type AxiWriteDmaDescAckType is record
183  valid : sl;
184  address : slv(63 downto 0);
185  dropEn : sl;
186  maxSize : slv(31 downto 0);
187  contEn : sl;
188  buffId : slv(15 downto 0);
189  end record;
190 
192  valid => '0',
193  address => (others=>'0'),
194  dropEn => '0',
195  maxSize => (others=>'0'),
196  contEn => '0',
197  buffId => (others=>'0')
198  );
199 
200  type AxiWriteDmaDescAckArray is array (natural range<>) of AxiWriteDmaDescAckType;
201 
202  constant AXI_WRITE_DMA_DESC_ACK_SIZE_C : integer := 114;
203 
204  function toSlv (r : AxiWriteDmaDescAckType ) return slv;
206 
207  -------------------------------------
208  -- DMA Write Descriptor Return (AxiStreamDmaV2)
209  -- Returned from dma engine when frame is complete
210  -------------------------------------
211 
212  type AxiWriteDmaDescRetType is record
213  valid : sl;
214  buffId : slv(15 downto 0);
215  firstUser : slv(7 downto 0);
216  lastUser : slv(7 downto 0);
217  size : slv(31 downto 0);
219  result : slv(2 downto 0);
220  dest : slv(7 downto 0);
221  id : slv(7 downto 0);
222  end record;
223 
225  valid => '0',
226  buffId => (others=>'0'),
227  firstUser => (others=>'0'),
228  lastUser => (others=>'0'),
229  size => (others=>'0'),
230  continue => '0',
231  result => (others=>'0'),
232  dest => (others=>'0'),
233  id => (others=>'0')
234  );
235 
236  type AxiWriteDmaDescRetArray is array (natural range<>) of AxiWriteDmaDescRetType;
237 
238  constant AXI_WRITE_DMA_DESC_RET_SIZE_C : integer := 84;
239 
240  function toSlv (r : AxiWriteDmaDescRetType ) return slv;
242 
243  -------------------------------------
244  -- DMA Write Tracking (AxiStreamDmaV2)
245  -- Memory entry for tracking an in progress transaction.
246  -------------------------------------
247 
248  type AxiWriteDmaTrackType is record
249  dest : slv(7 downto 0);
251  address : slv(63 downto 0);
252  maxSize : slv(31 downto 0);
253  size : slv(31 downto 0);
254  firstUser : slv(7 downto 0);
255  contEn : sl;
256  dropEn : sl;
257  id : slv(7 downto 0);
258  buffId : slv(15 downto 0);
259  overflow : sl;
260  end record;
261 
263  dest => (others=>'0'),
264  inUse => '0',
265  address => (others=>'0'),
266  maxSize => (others=>'0'),
267  size => (others=>'0'),
268  firstUser => (others=>'0'),
269  contEn => '0',
270  dropEn => '0',
271  id => (others=>'0'),
272  buffId => (others=>'0'),
273  overflow => '0'
274  );
275 
276  type AxiWriteDmaTrackArray is array (natural range<>) of AxiWriteDmaTrackType;
277 
278  constant AXI_WRITE_DMA_TRACK_SIZE_C : integer := 172;
279 
280  function toSlv (r : AxiWriteDmaTrackType ) return slv;
281  function toAxiWriteDmaTrack (din : slv ) return AxiWriteDmaTrackType;
282 
283  -------------------------------------
284  -- DMA Read Descriptor Request (AxiStreamDmaV2)
285  -- Passed to DMA engine to initiate a read.
286  -------------------------------------
287 
288  type AxiReadDmaDescReqType is record
289  valid : sl;
290  address : slv(63 downto 0);
291  buffId : slv(15 downto 0);
292  firstUser : slv(7 downto 0);
293  lastUser : slv(7 downto 0);
294  size : slv(31 downto 0);
295  continue : sl;
296  id : slv(7 downto 0);
297  dest : slv(7 downto 0);
298  end record;
299 
301  valid => '0',
302  address => (others=>'0'),
303  buffId => (others=>'0'),
304  firstUser => (others=>'0'),
305  lastUser => (others=>'0'),
306  size => (others=>'0'),
307  continue => '0',
308  id => (others=>'0'),
309  dest => (others=>'0')
310  );
311 
312  type AxiReadDmaDescReqArray is array (natural range<>) of AxiReadDmaDescReqType;
313 
314  constant AXI_READ_DMA_DESC_REQ_SIZE_C : integer := 145;
315 
316  function toSlv (r : AxiReadDmaDescReqType ) return slv;
318 
319  -------------------------------------
320  -- DMA Read Descriptor Return (AxiStreamDmaV2)
321  -- Returned from dma engine when frame is complete
322  -------------------------------------
323 
324  type AxiReadDmaDescRetType is record
325  valid : sl;
326  buffId : slv(15 downto 0);
327  result : slv(2 downto 0);
328  end record;
329 
331  valid => '0',
332  buffId => (others=>'0'),
333  result => (others=>'0')
334  );
335 
336  type AxiReadDmaDescRetArray is array (natural range<>) of AxiReadDmaDescRetType;
337 
338  constant AXI_READ_DMA_DESC_RET_SIZE_C : integer := 19;
339 
340  function toSlv (r : AxiReadDmaDescRetType ) return slv;
342 
343 end package AxiDmaPkg;
344 
345 package body AxiDmaPkg is
346 
347  function toSlv (r : AxiWriteDmaDescReqType ) return slv is
348  variable retValue : slv(AXI_WRITE_DMA_DESC_REQ_SIZE_C-1 downto 0) := (others => '0');
349  variable i : integer := 0;
350  begin
351  assignSlv(i, retValue, r.dest);
352  return(retValue);
353  end function;
354 
357  variable i : integer := 0;
358  begin
359  desc.valid := valid;
360  assignRecord(i, din, desc.dest);
361  return(desc);
362  end function;
363 
364  function toSlv (r : AxiWriteDmaDescAckType ) return slv is
365  variable retValue : slv(AXI_WRITE_DMA_DESC_ACK_SIZE_C-1 downto 0) := (others => '0');
366  variable i : integer := 0;
367  begin
368  assignSlv(i, retValue, r.address);
369  assignSlv(i, retValue, r.dropEn);
370  assignSlv(i, retValue, r.maxSize);
371  assignSlv(i, retValue, r.contEn);
372  assignSlv(i, retValue, r.buffId);
373  return(retValue);
374  end function;
375 
378  variable i : integer := 0;
379  begin
380  desc.valid := valid;
381  assignRecord(i, din, desc.address);
382  assignRecord(i, din, desc.dropEn);
383  assignRecord(i, din, desc.maxSize);
384  assignRecord(i, din, desc.contEn);
385  assignRecord(i, din, desc.buffId);
386  return(desc);
387  end function;
388 
389  function toSlv (r : AxiWriteDmaDescRetType ) return slv is
390  variable retValue : slv(AXI_WRITE_DMA_DESC_RET_SIZE_C-1 downto 0) := (others => '0');
391  variable i : integer := 0;
392  begin
393  assignSlv(i, retValue, r.buffId);
394  assignSlv(i, retValue, r.firstUser);
395  assignSlv(i, retValue, r.lastUser);
396  assignSlv(i, retValue, r.size);
397  assignSlv(i, retValue, r.continue);
398  assignSlv(i, retValue, r.result);
399  assignSlv(i, retValue, r.dest);
400  assignSlv(i, retValue, r.id);
401  return(retValue);
402  end function;
403 
406  variable i : integer := 0;
407  begin
408  desc.valid := valid;
409  assignRecord(i, din, desc.buffId);
410  assignRecord(i, din, desc.firstUser);
411  assignRecord(i, din, desc.lastUser);
412  assignRecord(i, din, desc.size);
413  assignRecord(i, din, desc.continue);
414  assignRecord(i, din, desc.result);
415  assignRecord(i, din, desc.dest);
416  assignRecord(i, din, desc.id);
417  return(desc);
418  end function;
419 
420  function toSlv (r : AxiWriteDmaTrackType ) return slv is
421  variable retValue : slv(AXI_WRITE_DMA_TRACK_SIZE_C-1 downto 0) := (others => '0');
422  variable i : integer := 0;
423  begin
424  assignSlv(i, retValue, r.dest);
425  assignSlv(i, retValue, r.inUse);
426  assignSlv(i, retValue, r.address);
427  assignSlv(i, retValue, r.maxSize);
428  assignSlv(i, retValue, r.size);
429  assignSlv(i, retValue, r.firstUser);
430  assignSlv(i, retValue, r.contEn);
431  assignSlv(i, retValue, r.dropEn);
432  assignSlv(i, retValue, r.id);
433  assignSlv(i, retValue, r.buffId);
434  assignSlv(i, retValue, r.overflow);
435  return(retValue);
436  end function;
437 
438  function toAxiWriteDmaTrack (din : slv) return AxiWriteDmaTrackType is
440  variable i : integer := 0;
441  begin
442  assignRecord(i, din, desc.dest);
443  assignRecord(i, din, desc.inUse);
444  assignRecord(i, din, desc.address);
445  assignRecord(i, din, desc.maxSize);
446  assignRecord(i, din, desc.size);
447  assignRecord(i, din, desc.firstUser);
448  assignRecord(i, din, desc.contEn);
449  assignRecord(i, din, desc.dropEn);
450  assignRecord(i, din, desc.id);
451  assignRecord(i, din, desc.buffId);
452  assignRecord(i, din, desc.overflow);
453  return(desc);
454  end function;
455 
456  function toSlv (r : AxiReadDmaDescReqType ) return slv is
457  variable retValue : slv(AXI_READ_DMA_DESC_REQ_SIZE_C-1 downto 0) := (others => '0');
458  variable i : integer := 0;
459  begin
460  assignSlv(i, retValue, r.address);
461  assignSlv(i, retValue, r.buffId);
462  assignSlv(i, retValue, r.firstUser);
463  assignSlv(i, retValue, r.lastUser);
464  assignSlv(i, retValue, r.size);
465  assignSlv(i, retValue, r.continue);
466  assignSlv(i, retValue, r.id);
467  assignSlv(i, retValue, r.dest);
468  return(retValue);
469  end function;
470 
471  function toAxiReadDmaDescReq (din : slv; valid : sl) return AxiReadDmaDescReqType is
473  variable i : integer := 0;
474  begin
475  desc.valid := valid;
476  assignRecord(i, din, desc.address);
477  assignRecord(i, din, desc.buffId);
478  assignRecord(i, din, desc.firstUser);
479  assignRecord(i, din, desc.lastUser);
480  assignRecord(i, din, desc.size);
481  assignRecord(i, din, desc.continue);
482  assignRecord(i, din, desc.id);
483  assignRecord(i, din, desc.dest);
484  return(desc);
485  end function;
486 
487  function toSlv (r : AxiReadDmaDescRetType ) return slv is
488  variable retValue : slv(AXI_READ_DMA_DESC_RET_SIZE_C-1 downto 0) := (others => '0');
489  variable i : integer := 0;
490  begin
491  assignSlv(i, retValue, r.buffId);
492  assignSlv(i, retValue, r.result);
493  return(retValue);
494  end function;
495 
496  function toAxiReadDmaDescRet (din : slv; valid : sl) return AxiReadDmaDescRetType is
498  variable i : integer := 0;
499  begin
500  desc.valid := valid;
501  assignRecord(i, din, desc.buffId);
502  assignRecord(i, din, desc.result);
503  return(desc);
504  end function;
505 
506 end package body AxiDmaPkg;
507 
array(natural range <> ) of AxiReadDmaReqType AxiReadDmaReqArray
Definition: AxiDmaPkg.vhd:126
integer := 172 AXI_WRITE_DMA_TRACK_SIZE_C
Definition: AxiDmaPkg.vhd:278
natural range 0 to 8 TDEST_BITS_C
slv( 63 downto 0) address
Definition: AxiDmaPkg.vhd:49
AxiWriteDmaDescAckType toAxiWriteDmaDescAckdin,valid,
Definition: AxiDmaPkg.vhd:205
slv( 7 downto 0) dest
Definition: AxiDmaPkg.vhd:78
sl overflow
Definition: AxiDmaPkg.vhd:73
sl readError
Definition: AxiDmaPkg.vhd:136
array(natural range <> ) of AxiWriteDmaDescReqType AxiWriteDmaDescReqArray
Definition: AxiDmaPkg.vhd:168
array(natural range <> ) of AxiReadDmaDescRetType AxiReadDmaDescRetArray
Definition: AxiDmaPkg.vhd:336
AxiReadDmaDescRetType :=(valid => '0',buffId =>( others => '0'),result =>( others => '0')) AXI_READ_DMA_DESC_RET_INIT_C
Definition: AxiDmaPkg.vhd:330
slv( 7 downto 0) firstUser
Definition: AxiDmaPkg.vhd:76
array(natural range <> ) of AxiReadDmaDescReqType AxiReadDmaDescReqArray
Definition: AxiDmaPkg.vhd:312
std_logic sl
Definition: StdRtlPkg.vhd:28
array(natural range <> ) of AxiWriteDmaDescAckType AxiWriteDmaDescAckArray
Definition: AxiDmaPkg.vhd:200
integer := 84 AXI_WRITE_DMA_DESC_RET_SIZE_C
Definition: AxiDmaPkg.vhd:238
slv( 7 downto 0) id
Definition: AxiDmaPkg.vhd:79
sl writeError
Definition: AxiDmaPkg.vhd:74
integer := 145 AXI_READ_DMA_DESC_REQ_SIZE_C
Definition: AxiDmaPkg.vhd:314
slv( 15 downto 0) buffId
Definition: AxiDmaPkg.vhd:188
natural range 1 to 16 TDATA_BYTES_C
integer := 114 AXI_WRITE_DMA_DESC_ACK_SIZE_C
Definition: AxiDmaPkg.vhd:202
AxiWriteDmaDescReqType
Definition: AxiDmaPkg.vhd:158
AxiWriteDmaTrackType toAxiWriteDmaTrackdin,
Definition: AxiDmaPkg.vhd:281
slv( 2 downto 0) result
Definition: AxiDmaPkg.vhd:219
AxiWriteDmaDescReqType :=(valid => '0',dest =>( others => '0')) AXI_WRITE_DMA_DESC_REQ_INIT_C
Definition: AxiDmaPkg.vhd:163
TkeepModeType TKEEP_MODE_C
AxiWriteDmaAckType
Definition: AxiDmaPkg.vhd:69
array(natural range <> ) of AxiWriteDmaDescRetType AxiWriteDmaDescRetArray
Definition: AxiDmaPkg.vhd:236
slv( 7 downto 0) lastUser
Definition: AxiDmaPkg.vhd:77
natural range 0 to 8 TID_BITS_C
AxiWriteDmaDescAckType
Definition: AxiDmaPkg.vhd:182
AxiReadDmaDescReqType toAxiReadDmaDescReqdin,valid,
Definition: AxiDmaPkg.vhd:317
AxiWriteDmaTrackType
Definition: AxiDmaPkg.vhd:248
slv toSlvr,
Definition: AxiDmaPkg.vhd:172
AxiReadDmaDescReqType :=(valid => '0',address =>( others => '0'),buffId =>( others => '0'),firstUser =>( others => '0'),lastUser =>( others => '0'),size =>( others => '0'),continue => '0',id =>( others => '0'),dest =>( others => '0')) AXI_READ_DMA_DESC_REQ_INIT_C
Definition: AxiDmaPkg.vhd:300
array(natural range <> ) of AxiWriteDmaTrackType AxiWriteDmaTrackArray
Definition: AxiDmaPkg.vhd:276
boolean TSTRB_EN_C
array(natural range <> ) of AxiWriteDmaAckType AxiWriteDmaAckArray
Definition: AxiDmaPkg.vhd:97
AxiWriteDmaReqType
Definition: AxiDmaPkg.vhd:46
AxiReadDmaReqType :=(request => '0',address =>( others => '0'),size =>( others => '0'),firstUser =>( others => '0'),lastUser =>( others => '0'),dest =>( others => '0'),id =>( others => '0')) AXI_READ_DMA_REQ_INIT_C
Definition: AxiDmaPkg.vhd:115
TUserModeType TUSER_MODE_C
AxiStreamConfigType :=(TSTRB_EN_C => false,TDATA_BYTES_C => 8,TDEST_BITS_C => 8,TID_BITS_C => 0,TKEEP_MODE_C => TKEEP_COMP_C,TUSER_BITS_C => 8,TUSER_MODE_C => TUSER_FIRST_LAST_C) AXIS_WRITE_DMA_CONFIG_C
Definition: AxiDmaPkg.vhd:32
AxiWriteDmaTrackType :=(dest =>( others => '0'),inUse => '0',address =>( others => '0'),maxSize =>( others => '0'),size =>( others => '0'),firstUser =>( others => '0'),contEn => '0',dropEn => '0',id =>( others => '0'),buffId =>( others => '0'),overflow => '0') AXI_WRITE_DMA_TRACK_INIT_C
Definition: AxiDmaPkg.vhd:262
natural range 0 to 8 TUSER_BITS_C
AxiWriteDmaAckType :=(idle => '1',done => '0',size =>( others => '0'),overflow => '0',writeError => '0',errorValue => "00",firstUser =>( others => '0'),lastUser =>( others => '0'),dest =>( others => '0'),id =>( others => '0')) AXI_WRITE_DMA_ACK_INIT_C
Definition: AxiDmaPkg.vhd:83
AxiReadDmaDescRetType toAxiReadDmaDescRetdin,valid,
Definition: AxiDmaPkg.vhd:341
AxiWriteDmaDescRetType :=(valid => '0',buffId =>( others => '0'),firstUser =>( others => '0'),lastUser =>( others => '0'),size =>( others => '0'),continue => '0',result =>( others => '0'),dest =>( others => '0'),id =>( others => '0')) AXI_WRITE_DMA_DESC_RET_INIT_C
Definition: AxiDmaPkg.vhd:224
AxiReadDmaDescReqType
Definition: AxiDmaPkg.vhd:288
AxiWriteDmaDescAckType :=(valid => '0',address =>( others => '0'),dropEn => '0',maxSize =>( others => '0'),contEn => '0',buffId =>( others => '0')) AXI_WRITE_DMA_DESC_ACK_INIT_C
Definition: AxiDmaPkg.vhd:191
AxiReadDmaAckType :=(idle => '1',done => '0',readError => '0',errorValue => "00") AXI_READ_DMA_ACK_INIT_C
Definition: AxiDmaPkg.vhd:141
slv( 31 downto 0) size
Definition: AxiDmaPkg.vhd:72
AxiWriteDmaDescRetType toAxiWriteDmaDescRetdin,valid,
Definition: AxiDmaPkg.vhd:241
slv( 1 downto 0) errorValue
Definition: AxiDmaPkg.vhd:75
slv( 31 downto 0) maxSize
Definition: AxiDmaPkg.vhd:50
integer := 8 AXI_WRITE_DMA_DESC_REQ_SIZE_C
Definition: AxiDmaPkg.vhd:170
AxiWriteDmaDescReqType toAxiWriteDmaDescReqdin,valid,
Definition: AxiDmaPkg.vhd:173
array(natural range <> ) of AxiReadDmaAckType AxiReadDmaAckArray
Definition: AxiDmaPkg.vhd:149
sl request
Definition: AxiDmaPkg.vhd:47
array(natural range <> ) of AxiWriteDmaReqType AxiWriteDmaReqArray
Definition: AxiDmaPkg.vhd:62
AxiWriteDmaDescRetType
Definition: AxiDmaPkg.vhd:212
integer := 19 AXI_READ_DMA_DESC_RET_SIZE_C
Definition: AxiDmaPkg.vhd:338
AxiReadDmaDescRetType
Definition: AxiDmaPkg.vhd:324
std_logic_vector slv
Definition: StdRtlPkg.vhd:29
AxiWriteDmaReqType :=(request => '0',drop => '0',address =>( others => '0'),maxSize =>( others => '0')) AXI_WRITE_DMA_REQ_INIT_C
Definition: AxiDmaPkg.vhd:54