1 ------------------------------------------------------------------------------- 2 -- File : AxiStreamDmaRead.vhd 3 -- Company : SLAC National Accelerator Laboratory 4 -- Created : 2013-05-06 5 -- Standard : VHDL'93/02 6 ------------------------------------------------------------------------------- 8 -- Package file for AXI DMA Controller 9 ------------------------------------------------------------------------------- 10 -- This file is part of 'SLAC Firmware Standard Library'. 11 -- It is subject to the license terms in the LICENSE.txt file found in the 12 -- top-level directory of this distribution and at: 13 -- https://confluence.slac.stanford.edu/display/ppareg/LICENSE.html. 14 -- No part of 'SLAC Firmware Standard Library', including this file, 15 -- may be copied, modified, propagated, or distributed except according to 16 -- the terms contained in the LICENSE.txt file. 17 ------------------------------------------------------------------------------- 20 use ieee.std_logic_1164.
all;
29 ------------------------------------- 30 -- Write DMA Axi-Stream Configuration 31 ------------------------------------- 41 ------------------------------------- 42 -- Write DMA Request (AxiStreamDmaWrite) 43 ------------------------------------- 53 -- Initialization constants 64 ------------------------------------- 65 -- Write DMA Acknowledge (AxiStreamDmaWrite) 66 ------------------------------------- 82 -- Initialization constants 86 size => (others=>'0'), 92 dest => (others=>'0'), 99 ------------------------------------- 100 -- Read DMA Request (AxiStreamDmaRead) 101 ------------------------------------- 111 id : slv(7 downto 0);
114 -- Initialization constants 118 size => (others=>'0'), 121 dest => (others=>'0'), 128 ------------------------------------- 129 -- Read DMA Acknowledge (AxiStreamDmaRead) 130 ------------------------------------- 140 -- Initialization constants 152 ------------------------------------- 153 -- DMA Write Descriptor Request (AxiStreamDmaV2) 154 -- Issued from dma write engine to request a free 155 -- descriptor from the pool. 156 ------------------------------------- 165 dest => (others=>'0') 176 ------------------------------------- 177 -- DMA Write Descriptor Ack (AxiStreamDmaV2) 178 -- Returned to dma write engine in response to 179 -- AxiWriteDescReqType. 180 ------------------------------------- 207 ------------------------------------- 208 -- DMA Write Descriptor Return (AxiStreamDmaV2) 209 -- Returned from dma engine when frame is complete 210 ------------------------------------- 221 id : slv(7 downto 0);
229 size => (others=>'0'), 232 dest => (others=>'0'), 243 ------------------------------------- 244 -- DMA Write Tracking (AxiStreamDmaV2) 245 -- Memory entry for tracking an in progress transaction. 246 ------------------------------------- 257 id : slv(7 downto 0);
263 dest => (others=>'0'), 267 size => (others=>'0'), 283 ------------------------------------- 284 -- DMA Read Descriptor Request (AxiStreamDmaV2) 285 -- Passed to DMA engine to initiate a read. 286 ------------------------------------- 296 id : slv(7 downto 0);
306 size => (others=>'0'), 309 dest => (others=>'0') 319 ------------------------------------- 320 -- DMA Read Descriptor Return (AxiStreamDmaV2) 321 -- Returned from dma engine when frame is complete 322 ------------------------------------- 343 end package AxiDmaPkg;
351 assignSlv
(i, retValue, r.
dest);
360 assignRecord
(i, din, desc.
dest);
368 assignSlv
(i, retValue, r.
address);
369 assignSlv
(i, retValue, r.
dropEn);
370 assignSlv
(i, retValue, r.
maxSize);
371 assignSlv
(i, retValue, r.
contEn);
372 assignSlv
(i, retValue, r.
buffId);
381 assignRecord
(i, din, desc.
address);
382 assignRecord
(i, din, desc.
dropEn);
383 assignRecord
(i, din, desc.
maxSize);
384 assignRecord
(i, din, desc.
contEn);
385 assignRecord
(i, din, desc.
buffId);
393 assignSlv
(i, retValue, r.
buffId);
396 assignSlv
(i, retValue, r.
size);
398 assignSlv
(i, retValue, r.
result);
399 assignSlv
(i, retValue, r.
dest);
400 assignSlv
(i, retValue, r.
id);
409 assignRecord
(i, din, desc.
buffId);
411 assignRecord
(i, din, desc.
lastUser);
412 assignRecord
(i, din, desc.
size);
413 assignRecord
(i, din, desc.
continue);
414 assignRecord
(i, din, desc.
result);
415 assignRecord
(i, din, desc.
dest);
416 assignRecord
(i, din, desc.
id);
424 assignSlv
(i, retValue, r.
dest);
425 assignSlv
(i, retValue, r.
inUse);
426 assignSlv
(i, retValue, r.
address);
427 assignSlv
(i, retValue, r.
maxSize);
428 assignSlv
(i, retValue, r.
size);
430 assignSlv
(i, retValue, r.
contEn);
431 assignSlv
(i, retValue, r.
dropEn);
432 assignSlv
(i, retValue, r.
id);
433 assignSlv
(i, retValue, r.
buffId);
442 assignRecord
(i, din, desc.
dest);
443 assignRecord
(i, din, desc.
inUse);
444 assignRecord
(i, din, desc.
address);
445 assignRecord
(i, din, desc.
maxSize);
446 assignRecord
(i, din, desc.
size);
448 assignRecord
(i, din, desc.
contEn);
449 assignRecord
(i, din, desc.
dropEn);
450 assignRecord
(i, din, desc.
id);
451 assignRecord
(i, din, desc.
buffId);
452 assignRecord
(i, din, desc.
overflow);
460 assignSlv
(i, retValue, r.
address);
461 assignSlv
(i, retValue, r.
buffId);
464 assignSlv
(i, retValue, r.
size);
466 assignSlv
(i, retValue, r.
id);
467 assignSlv
(i, retValue, r.
dest);
476 assignRecord
(i, din, desc.
address);
477 assignRecord
(i, din, desc.
buffId);
479 assignRecord
(i, din, desc.
lastUser);
480 assignRecord
(i, din, desc.
size);
481 assignRecord
(i, din, desc.
continue);
482 assignRecord
(i, din, desc.
id);
483 assignRecord
(i, din, desc.
dest);
491 assignSlv
(i, retValue, r.
buffId);
492 assignSlv
(i, retValue, r.
result);
501 assignRecord
(i, din, desc.
buffId);
502 assignRecord
(i, din, desc.
result);
506 end package body AxiDmaPkg;
array(natural range <> ) of AxiReadDmaReqType AxiReadDmaReqArray
integer := 172 AXI_WRITE_DMA_TRACK_SIZE_C
natural range 0 to 8 TDEST_BITS_C
slv( 63 downto 0) address
AxiWriteDmaDescAckType toAxiWriteDmaDescAckdin,valid,
array(natural range <> ) of AxiWriteDmaDescReqType AxiWriteDmaDescReqArray
array(natural range <> ) of AxiReadDmaDescRetType AxiReadDmaDescRetArray
AxiReadDmaDescRetType :=(valid => '0',buffId =>( others => '0'),result =>( others => '0')) AXI_READ_DMA_DESC_RET_INIT_C
slv( 7 downto 0) firstUser
array(natural range <> ) of AxiReadDmaDescReqType AxiReadDmaDescReqArray
array(natural range <> ) of AxiWriteDmaDescAckType AxiWriteDmaDescAckArray
integer := 84 AXI_WRITE_DMA_DESC_RET_SIZE_C
integer := 145 AXI_READ_DMA_DESC_REQ_SIZE_C
natural range 1 to 16 TDATA_BYTES_C
integer := 114 AXI_WRITE_DMA_DESC_ACK_SIZE_C
AxiWriteDmaTrackType toAxiWriteDmaTrackdin,
AxiWriteDmaDescReqType :=(valid => '0',dest =>( others => '0')) AXI_WRITE_DMA_DESC_REQ_INIT_C
TkeepModeType TKEEP_MODE_C
array(natural range <> ) of AxiWriteDmaDescRetType AxiWriteDmaDescRetArray
slv( 7 downto 0) lastUser
natural range 0 to 8 TID_BITS_C
AxiReadDmaDescReqType toAxiReadDmaDescReqdin,valid,
AxiReadDmaDescReqType :=(valid => '0',address =>( others => '0'),buffId =>( others => '0'),firstUser =>( others => '0'),lastUser =>( others => '0'),size =>( others => '0'),continue => '0',id =>( others => '0'),dest =>( others => '0')) AXI_READ_DMA_DESC_REQ_INIT_C
array(natural range <> ) of AxiWriteDmaTrackType AxiWriteDmaTrackArray
array(natural range <> ) of AxiWriteDmaAckType AxiWriteDmaAckArray
AxiReadDmaReqType :=(request => '0',address =>( others => '0'),size =>( others => '0'),firstUser =>( others => '0'),lastUser =>( others => '0'),dest =>( others => '0'),id =>( others => '0')) AXI_READ_DMA_REQ_INIT_C
TUserModeType TUSER_MODE_C
AxiStreamConfigType :=(TSTRB_EN_C => false,TDATA_BYTES_C => 8,TDEST_BITS_C => 8,TID_BITS_C => 0,TKEEP_MODE_C => TKEEP_COMP_C,TUSER_BITS_C => 8,TUSER_MODE_C => TUSER_FIRST_LAST_C) AXIS_WRITE_DMA_CONFIG_C
AxiWriteDmaTrackType :=(dest =>( others => '0'),inUse => '0',address =>( others => '0'),maxSize =>( others => '0'),size =>( others => '0'),firstUser =>( others => '0'),contEn => '0',dropEn => '0',id =>( others => '0'),buffId =>( others => '0'),overflow => '0') AXI_WRITE_DMA_TRACK_INIT_C
natural range 0 to 8 TUSER_BITS_C
AxiWriteDmaAckType :=(idle => '1',done => '0',size =>( others => '0'),overflow => '0',writeError => '0',errorValue => "00",firstUser =>( others => '0'),lastUser =>( others => '0'),dest =>( others => '0'),id =>( others => '0')) AXI_WRITE_DMA_ACK_INIT_C
AxiReadDmaDescRetType toAxiReadDmaDescRetdin,valid,
AxiWriteDmaDescRetType :=(valid => '0',buffId =>( others => '0'),firstUser =>( others => '0'),lastUser =>( others => '0'),size =>( others => '0'),continue => '0',result =>( others => '0'),dest =>( others => '0'),id =>( others => '0')) AXI_WRITE_DMA_DESC_RET_INIT_C
AxiWriteDmaDescAckType :=(valid => '0',address =>( others => '0'),dropEn => '0',maxSize =>( others => '0'),contEn => '0',buffId =>( others => '0')) AXI_WRITE_DMA_DESC_ACK_INIT_C
AxiReadDmaAckType :=(idle => '1',done => '0',readError => '0',errorValue => "00") AXI_READ_DMA_ACK_INIT_C
AxiWriteDmaDescRetType toAxiWriteDmaDescRetdin,valid,
slv( 1 downto 0) errorValue
slv( 31 downto 0) maxSize
integer := 8 AXI_WRITE_DMA_DESC_REQ_SIZE_C
AxiWriteDmaDescReqType toAxiWriteDmaDescReqdin,valid,
array(natural range <> ) of AxiReadDmaAckType AxiReadDmaAckArray
array(natural range <> ) of AxiWriteDmaReqType AxiWriteDmaReqArray
integer := 19 AXI_READ_DMA_DESC_RET_SIZE_C
AxiWriteDmaReqType :=(request => '0',drop => '0',address =>( others => '0'),maxSize =>( others => '0')) AXI_WRITE_DMA_REQ_INIT_C