pgp-pcie-apps Documentation

DOE Code

Firmware and software for moving data between PGP-protocol optical links (typically connected to detectors) and a PCIe DMA engine. Virtual channels and higher-level routing are owned by the software stack; this repo provides the PGP↔DMA/AXI-PCIe plumbing and the board-specific target designs that build into .bit and .mcs artefacts.

The repository is hardware-agnostic and supports multiple Xilinx carrier boards via the firmware/targets/ tree.

Features

• Protocol-lane handlers for PGP2b / PGP3 / PGP4 and HTSP 100G, built on surf.

• AXI-PCIe DMA integration via axi-pcie-core — see the axi-pcie-core documentation.

• PyRogue-based scripts under software/scripts/ for register access, monitoring, PRBS testing, and on-the-fly FPGA reprogramming.

Getting Started

• First build — First Build — XilinxVariumC1100DmaLoopback walks through cloning the repo, sourcing Vivado, and building XilinxVariumC1100DmaLoopback end to end.

• Load the PCIe driver — Load the PCIe Kernel Driver covers the aes-stream-drivers datadev.ko build and load procedure.

• Reprogram an installed card — Program a Board with updatePcieFpga.py covers updatePcieFpga.py.

Contents:

• Tutorials
  • First Build — XilinxVariumC1100DmaLoopback
  • Building XilinxVariumC1100PrbsTester
  • Run the DMA Loopback Test
• How-To Guides
  • Load the PCIe Kernel Driver
  • Add a New Board Target
  • Add a New Line Rate
  • Select a Protocol — PGP2b vs PGP3 vs PGP4 vs HTSP
  • Program a Board with updatePcieFpga.py
  • Run the PGP Test Suite
  • Simulate the DMA Loopback Path
• Reference
  • Supported Targets
  • Directory Layout
  • PyRogue Scripts
  • Makefile Targets
  • AXI-Lite Address Map
• Explanation
  • Architecture
  • Data Flow
  • Protocol Variants
  • Clock Domains
  • Relation to axi-pcie-core