Explanation

Narrative material on why pgp-pcie-apps is structured the way it is — the layered protocol decomposition, the data-flow conventions, the relationship with axi-pcie-core and surf.

Explanation

• Architecture
  • The Three Layers
  • What axi-pcie-core Provides Underneath
  • Bus Conventions
  • GT-Family Selection
• Data Flow
  • PGP RX Path (Optical → Host DMA)
  • PGP TX Path (Host DMA → Optical)
  • AXI-Lite Register Path (Software → Firmware Registers)
  • Back-Pressure Path (DMA Pause → PGP Pause)
  • State
• Protocol Variants
  • Common Contract
  • PGP2b
  • PGP3
  • PGP4
  • HTSP
  • Trade-Off Summary
• Clock Domains
  • The Three Domains
  • Crossings
  • Why dmaClk is 250 MHz
  • Implications for Application Design
• Relation to axi-pcie-core
  • What Lives Where
  • How They Interact
  • When to Update Which Repo
  • Version Coordination