sfixedPreAddMultAdd.rtl Architecture Reference

Architecture >> sfixedPreAddMultAdd::rtl

Processes
comb	( a , aVld , b , bVld , c , cVld , d , dVld , r )
seq	( clk )

Constants
PRE_ADD_HIGH_C	integer := maximum ( a ' high , d ' high ) + 1
PRE_ADD_LOW_C	integer := minimum ( a ' low , d ' low )
REG_INIT_C	RegType := ( areg = > ( others = > ' 0 ' ) , dreg = > ( others = > ' 0 ' ) , breg = > ( others = > ' 0 ' ) , brreg = > ( others = > ' 0 ' ) , creg = > ( others = > ' 0 ' ) , crreg = > ( others = > ' 0 ' ) , crrreg = > ( others = > ' 0 ' ) , preAdd = > ( others = > ' 0 ' ) , mreg = > ( others = > ' 0 ' ) , preg = > ( others = > ( others = > ' 0 ' ) ) , vld = > ( others = > ' 0 ' ) )

Types
sfixedArray	array ( natural range <> ) of sfixed

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following file:

• dsp/fixed/SfixedPreAddMultAdd.vhd