sfixedMult.rtl Architecture Reference

Architecture >> sfixedMult::rtl

Processes
comb	( a , aVld , b , bVld , c , r )
seq	( clk )

Constants
C_HIGH_BIT_C	integer := a ' high+ b ' high+ 1
C_LOW_BIT_C	integer := a ' low+ b ' low
REG_INIT_C	RegType := ( areg = > ( others = > ' 0 ' ) , breg = > ( others = > ' 0 ' ) , mreg = > ( others = > ' 0 ' ) , preg = > ( others = > ( others = > ' 0 ' ) ) , vld = > ( others = > ' 0 ' ) )

Types
sfixedArray	array ( natural range <> ) of sfixed

Signals
c	sfixed ( C_HIGH_BIT_C downto C_LOW_BIT_C ) := ( others = > ' 0 ' )
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following file:

• dsp/fixed/SfixedMult.vhd