iq16bTo32b.rtl Architecture Reference

Architecture >> iq16bTo32b::rtl

Processes
comb	( dataInI , dataInQ , r , validIn , wrRst )
seq	( wrClk )
comb	( dataInI , dataInQ , r , validIn , wrRst )
seq	( wrClk )

Constants
REG_INIT_C	RegType := ( wordSel = > ' 0 ' , wrEn = > ' 0 ' , dataI = > ( others = > ' 0 ' ) , dataQ = > ( others = > ' 0 ' ) )

Signals
r	RegType := REG_INIT_C
rin	RegType
s_valid	sl

Records
RegType

Instantiations
u_fifo	Fifo <Entity Fifo>
u_fifo	Fifo <Entity Fifo>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/iq16bTo32b.vhd
• protocols/jesd204b/rtl/iq16bTo32b.vhd