csa3.rtl Architecture Reference

Architecture >> csa3::rtl

Processes
comb	( a , b , c , inputA , inputB , inputC , r , sum )
seq	( clk )

Constants
INT_OVERFLOW_STYLE_C	fixed_overflow_style_type := fixed_wrap
INT_ROUNDING_STYLE_C	fixed_round_style_type := fixed_truncate
HIGH_ARRAY_C	IntegerArray ( 2 downto 0 ) := ( 0 = > a ' high , 1 = > b ' high , 2 = > c ' high )
LOW_ARRAY_C	IntegerArray ( 2 downto 0 ) := ( 0 = > a ' low , 1 = > b ' low , 2 = > c ' low )
HIGH_BIT_C	integer := maximum ( HIGH_ARRAY_C ) + EXTRA_MSB_G
MED_BIT_C	integer := median ( LOW_ARRAY_C )
LOW_BIT_C	integer := minimum ( LOW_ARRAY_C )
REG_INIT_C	RegType := ( a = > ( others = > ' 0 ' ) , b = > ( others = > ' 0 ' ) , c = > ( others = > ' 0 ' ) , sum = > ( others = > ' 0 ' ) )
I0	bit_vector ( 63 downto 0 ) := X " AAAAAAAAAAAAAAAA "
I1	bit_vector ( 63 downto 0 ) := X " CCCCCCCCCCCCCCCC "
I2	bit_vector ( 63 downto 0 ) := X " F0F0F0F0F0F0F0F0 " xor ( 63 downto 0 = > bit ' val ( boolean ' pos ( NEGATIVE_B_G ) ) )
I3	bit_vector ( 63 downto 0 ) := X " FF00FF00FF00FF00 " xor ( 63 downto 0 = > bit ' val ( boolean ' pos ( NEGATIVE_A_G ) ) )
I4	bit_vector ( 63 downto 0 ) := X " FFFF0000FFFF0000 "
I5	bit_vector ( 63 downto 0 ) := X " FFFFFFFF00000000 "

Signals
r	RegType := REG_INIT_C
rin	RegType
inputA	sfixed ( HIGH_BIT_C downto LOW_BIT_C )
inputB	sfixed ( HIGH_BIT_C downto LOW_BIT_C )
inputC	sfixed ( HIGH_BIT_C downto LOW_BIT_C )
sum	sfixed ( HIGH_BIT_C downto LOW_BIT_C )
O5	signed ( HIGH_BIT_C- MED_BIT_C+ 1 downto 0 )
O6	signed ( HIGH_BIT_C- MED_BIT_C downto 0 )
CY	slv ( ( HIGH_BIT_C- MED_BIT_C+ 1 + 7 ) / 8 * 8 downto 0 )
SI	slv ( ( HIGH_BIT_C- MED_BIT_C+ 1 + 7 ) / 8 * 8 - 1 downto 0 )
DI	slv ( ( HIGH_BIT_C- MED_BIT_C+ 1 + 7 ) / 8 * 8 - 1 downto 0 )
O	slv ( ( HIGH_BIT_C- MED_BIT_C+ 1 + 7 ) / 8 * 8 - 1 downto 0 )

Records
RegType

Instantiations
l6	lut6_2
c8	carry8

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The documentation for this design unit was generated from the following file:

• dsp/xilinx/fixed/Csa3.vhd