Architecture >> csa3::rtl
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comb | ( a , b , c , inputA , inputB , inputC , r , sum ) |
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seq | ( clk ) |
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INT_OVERFLOW_STYLE_C | fixed_overflow_style_type := fixed_wrap |
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INT_ROUNDING_STYLE_C | fixed_round_style_type := fixed_truncate |
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HIGH_ARRAY_C | IntegerArray ( 2 downto 0 ) := ( 0 = > a ' high , 1 = > b ' high , 2 = > c ' high ) |
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LOW_ARRAY_C | IntegerArray ( 2 downto 0 ) := ( 0 = > a ' low , 1 = > b ' low , 2 = > c ' low ) |
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HIGH_BIT_C | integer := maximum ( HIGH_ARRAY_C ) + EXTRA_MSB_G |
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MED_BIT_C | integer := median ( LOW_ARRAY_C ) |
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LOW_BIT_C | integer := minimum ( LOW_ARRAY_C ) |
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REG_INIT_C | RegType := ( a = > ( others = > ' 0 ' ) , b = > ( others = > ' 0 ' ) , c = > ( others = > ' 0 ' ) , sum = > ( others = > ' 0 ' ) ) |
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I0 | bit_vector ( 63 downto 0 ) := X " AAAAAAAAAAAAAAAA " |
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I1 | bit_vector ( 63 downto 0 ) := X " CCCCCCCCCCCCCCCC " |
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I2 | bit_vector ( 63 downto 0 ) := X " F0F0F0F0F0F0F0F0 " xor ( 63 downto 0 = > bit ' val ( boolean ' pos ( NEGATIVE_B_G ) ) ) |
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I3 | bit_vector ( 63 downto 0 ) := X " FF00FF00FF00FF00 " xor ( 63 downto 0 = > bit ' val ( boolean ' pos ( NEGATIVE_A_G ) ) ) |
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I4 | bit_vector ( 63 downto 0 ) := X " FFFF0000FFFF0000 " |
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I5 | bit_vector ( 63 downto 0 ) := X " FFFFFFFF00000000 " |
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r | RegType := REG_INIT_C |
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rin | RegType |
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inputA | sfixed ( HIGH_BIT_C downto LOW_BIT_C ) |
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inputB | sfixed ( HIGH_BIT_C downto LOW_BIT_C ) |
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inputC | sfixed ( HIGH_BIT_C downto LOW_BIT_C ) |
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sum | sfixed ( HIGH_BIT_C downto LOW_BIT_C ) |
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O5 | signed ( HIGH_BIT_C- MED_BIT_C+ 1 downto 0 ) |
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O6 | signed ( HIGH_BIT_C- MED_BIT_C downto 0 ) |
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CY | slv ( ( HIGH_BIT_C- MED_BIT_C+ 1 + 7 ) / 8 * 8 downto 0 ) |
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SI | slv ( ( HIGH_BIT_C- MED_BIT_C+ 1 + 7 ) / 8 * 8 - 1 downto 0 ) |
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DI | slv ( ( HIGH_BIT_C- MED_BIT_C+ 1 + 7 ) / 8 * 8 - 1 downto 0 ) |
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O | slv ( ( HIGH_BIT_C- MED_BIT_C+ 1 + 7 ) / 8 * 8 - 1 downto 0 ) |
The documentation for this design unit was generated from the following file:
1.9.8