cfixedMultAdd.rtl Architecture Reference

Architecture >> cfixedMultAdd::rtl

Processes
comb	( a , aVld , b , bVld , c , cVld , r , y )
seq	( clk )

Constants
DELAY_C	natural := 4 + ite ( REG_OUT_G , 1 , 0 )
M_LOW_C	integer := a.re ' low+ b.re ' low
M_HIGH_C	integer := a.re ' high+ b.re ' high+ 1
P_W_C	integer := 48
P_LOW_C	integer := a.re ' low+ b.re ' low
P_HIGH_C	integer := P_W_C+ P_LOW_C- 1
INT_OVERFLOW_STYLE_C	fixed_overflow_style_type := fixed_wrap
INT_ROUNDING_STYLE_C	fixed_round_style_type := fixed_truncate
REG_INIT_C	RegType := ( areg = > ( others = > ( others = > ( others = > ' 0 ' ) ) ) , breg = > ( others = > ( others = > ( others = > ' 0 ' ) ) ) , creg = > ( others = > ( others = > ( others = > ' 0 ' ) ) ) , m_rr = > ( others = > ' 0 ' ) , m_ii = > ( others = > ' 0 ' ) , m_ri = > ( others = > ' 0 ' ) , m_ir = > ( others = > ' 0 ' ) , p_rr = > ( others = > ' 0 ' ) , p_ii = > ( others = > ' 0 ' ) , p_ri = > ( others = > ' 0 ' ) , p_ir = > ( others = > ' 0 ' ) , y = > ( others = > ( others = > ' 0 ' ) ) , yVld = > ( others = > ' 0 ' ) )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following file:

• dsp/xilinx/fixed/CfixedMultAdd.vhd