TrueDualPortRamXpm.rtl Architecture Reference

Architecture >> TrueDualPortRamXpm::rtl

Constants
READ_LATENCY_A_C	natural := ite ( READ_LATENCY_A_G< 0 , READ_LATENCY_G , READ_LATENCY_A_G )
READ_LATENCY_B_C	natural := ite ( READ_LATENCY_B_G< 0 , READ_LATENCY_G , READ_LATENCY_B_G )

Signals
resetA	sl
resetB	sl
douta_xpm	slv ( DATA_WIDTH_G- 1 downto 0 )
doutb_xpm	slv ( DATA_WIDTH_G- 1 downto 0 )

Instantiations
u_ram	xpm_memory_tdpram

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The documentation for this design unit was generated from the following file:

• base/ram/xilinx/TrueDualPortRamXpm.vhd