TenGigEthGthUltraScaleClk.mapping Architecture Reference

Architecture >> TenGigEthGthUltraScaleClk::mapping

Signals
refClk	sl
refClkCopy	sl
refClock	sl
coreClock	sl
qpllReset	slv ( 1 downto 0 )
qpllReset	sl
dummyBits	slv ( 2 downto 0 )

Instantiations
ibufds_gte3_inst	ibufds_gte4
bufg_gt_inst	bufg_gt
gthultrascalequadpll_inst	GthUltraScaleQuadPll <Entity GthUltraScaleQuadPll>
ibufds_gte3_inst	ibufds_gte3
bufg_gt_inst	bufg_gt
gthultrascalequadpll_inst	GthUltraScaleQuadPll <Entity GthUltraScaleQuadPll>

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The documentation for this design unit was generated from the following files:

• ethernet/TenGigEthCore/gthUltraScale+/rtl/TenGigEthGthUltraScaleClk.vhd
• ethernet/TenGigEthCore/gthUltraScale/rtl/TenGigEthGthUltraScaleClk.vhd