SyncTrigRateVector Entity Reference

Inheritance diagram for SyncTrigRateVector:

Collaboration diagram for SyncTrigRateVector:

Entities
SyncTrigRateVector.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
StdRtlPkg	Package <StdRtlPkg>

Generics
TPD_G	time := 1 ns
RST_ASYNC_G	boolean := false
COMMON_CLK_G	boolean := false
ONE_SHOT_G	boolean := false
IN_POLARITY_G	slv := " 1 "
REF_CLK_FREQ_G	real := 200 . 0E + 6
REFRESH_RATE_G	real := 1 . 0E + 0
CNT_WIDTH_G	positive := 32
WIDTH_G	positive := 16

Ports
trigIn	in	slv ( WIDTH_G- 1 downto 0 )
trigRateUpdated	out	sl
trigRateOut	out	SlVectorArray ( WIDTH_G- 1 downto 0 , CNT_WIDTH_G- 1 downto 0 )
locClkEn	in	sl := ' 1 '
locClk	in	sl
refClk	in	sl

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The documentation for this design unit was generated from the following files:

• base/sync/rtl/SyncTrigRateVector.vhd
• build/SRC_VHDL/surf/SyncTrigRateVector.vhd