SugoiManagerRx7Series Entity Reference

Inheritance diagram for SugoiManagerRx7Series:

Entities
SugoiManagerRx7Series.mapping	architecture

Libraries
ieee
surf
unisim

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
vcomponents

Generics
TPD_G	time := 1 ns
DIFF_PAIR_G	boolean := true
DEVICE_FAMILY_G	string := " 7SERIES "
IODELAY_GROUP_G	string := " DESER_GROUP "
REF_FREQ_G	real := 300 . 0

Ports
clk	in	sl := ' 0 '
rst	in	sl := ' 0 '
rxP	in	sl := ' 0 '
rxN	in	sl := ' 0 '
dlyLoad	in	sl := ' 0 '
dlyCfg	in	slv ( 8 downto 0 ) := ( others = > ' 0 ' )
inv	in	sl := ' 0 '
rx	out	sl := ' 0 '

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SugoiManagerRx7SeriesDummy.vhd
• protocols/sugoi/rtl/7Series/SugoiManagerRx7Series.vhd
• protocols/sugoi/rtl/dummy/SugoiManagerRx7SeriesDummy.vhd