SspEncoder8b10bTb.sim Architecture Reference

Architecture >> SspEncoder8b10bTb::sim

Processes
WaveGen_Proc
WaveGen_Proc

Constants
TPD_G	time := 1 ns
RST_POLARITY_G	sl := ' 0 '
RST_ASYNC_G	boolean := true

Signals
clk	sl := ' 0 '
rst	sl := RST_POLARITY_G
validIn	sl := ' 0 '
dataIn	slv ( 15 downto 0 ) := ( others = > ' 0 ' )
encData	slv ( 19 downto 0 )
dataOut	slv ( 15 downto 0 )
validOut	sl
sof	sl
eof	sl
eofe	sl

Instantiations
encoder	SspEncoder8b10b <Entity SspEncoder8b10b>
decoder	SspDecoder8b10b <Entity SspDecoder8b10b>
encoder	SspEncoder8b10b <Entity SspEncoder8b10b>
decoder	SspDecoder8b10b <Entity SspDecoder8b10b>

---

The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SspEncoder8b10bTb.vhd
• protocols/ssp/tb/SspEncoder8b10bTb.vhd