SsiDbgTap.rtl Architecture Reference

Architecture >> SsiDbgTap::rtl

Processes
comb	( axisMaster , axisRst , axisSlave , r )
seq	( axisClk , axisRst )
comb	( axisMaster , axisRst , axisSlave , r )
seq	( axisClk , axisRst )

Constants
REG_INIT_C	RegType := ( cnt = > ( others = > ' 0 ' ) , copy = > AXI_STREAM_MASTER_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , MOVE_S )

Signals
r	RegType := REG_INIT_C
rin	RegType

Attributes
dont_touch	string
dont_touch	signal is " TRUE "

Records
RegType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SsiDbgTap.vhd
• protocols/ssi/rtl/SsiDbgTap.vhd