SsiCmdMasterPulser.rtl Architecture Reference

Architecture >> SsiCmdMasterPulser::rtl

Processes
PROCESS_157	( locClk , locRst )
PROCESS_363	( locClk , locRst )

Signals
pulse	sl := ' 0 '
cnt	positive range 1 to ( PULSE_WIDTH_G+ 1 ) := 1

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SsiCmdMasterPulser.vhd
• protocols/ssi/rtl/SsiCmdMasterPulser.vhd