SlaveRamIpIntegrator Entity Reference

Entities
SlaveRamIpIntegrator.mapping	architecture

Libraries
ieee

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned

Generics
INTERFACENAME	string := " S_RAM "
READ_LATENCY	natural range 0 to 3 := 1
ADDR_WIDTH	positive := 5
DATA_WIDTH	positive := 32

Ports
S_RAM_CLK	in	std_logic := ' 0 '
S_RAM_EN	in	std_logic := ' 1 '
S_RAM_WE	in	std_logic_vector ( ( DATA_WIDTH/ 8 ) - 1 downto 0 ) := ( others = > ' 0 ' )
S_RAM_RST	in	std_logic := ' 0 '
S_RAM_ADDR	in	std_logic_vector ( ADDR_WIDTH- 1 downto 0 ) := ( others = > ' 0 ' )
S_RAM_DIN	in	std_logic_vector ( DATA_WIDTH- 1 downto 0 ) := ( others = > ' 0 ' )
S_RAM_DOUT	out	std_logic_vector ( DATA_WIDTH- 1 downto 0 )
clk	out	std_logic
en	out	std_logic
we	out	std_logic_vector ( ( DATA_WIDTH/ 8 ) - 1 downto 0 )
rst	out	std_logic
addr	out	std_logic_vector ( ADDR_WIDTH- 1 downto 0 )
din	out	std_logic_vector ( DATA_WIDTH- 1 downto 0 )
dout	in	std_logic_vector ( DATA_WIDTH- 1 downto 0 ) := ( others = > ' 0 ' )

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The documentation for this design unit was generated from the following file:

• base/general/ip_integrator/SlaveRamIpIntegrator.vhd