SinCosLutTb.test Architecture Reference

Architecture >> SinCosLutTb::test

Processes
p_clk
p_cnt	( clk )

Constants
PHASE_WIDTH_C	integer := 18
CLK_PERIOD_C	time := 10 ns
ERROR_TOL_C	real := 0 . 0001
RUN_CNT_C	integer := 100 + 2 ** PHASE_WIDTH_C

Signals
clk	std_logic := ' 0 '
rst	std_logic := ' 1 '
run	boolean := true
cnt	integer := 0
phaseIn	unsigned ( PHASE_WIDTH_C- 1 downto 0 ) := ( others = > ' 0 ' )
validIn	sl := ' 0 '
dout	cfixed ( re ( 0 downto - 17 ) , im ( 0 downto - 17 ) )
validOut	sl := ' 0 '
doutRe	real := 0 . 0
doutIm	real := 0 . 0

Instantiations
u_dut	SinCosTaylor <Entity SinCosTaylor>

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The documentation for this design unit was generated from the following file:

• dsp/xilinx/tb/SinCosLutTb.vhd