SimpleDualPortRamXpm.rtl Architecture Reference

Architecture >> SimpleDualPortRamXpm::rtl

Signals
resetB	sl
doutb_xpm	slv ( DATA_WIDTH_G- 1 downto 0 )

Instantiations
u_ram	xpm_memory_sdpram

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The documentation for this design unit was generated from the following file:

• base/ram/xilinx/SimpleDualPortRamXpm.vhd