SaciMasterSync.rtl Architecture Reference

Architecture >> SaciMasterSync::rtl

Processes
saci_clk_p	( clk )
fall	( clk , rst )
seq	( clk , rst )
comb	( r , saciClkRising , saciMasterIn , saciRspFall )
saci_clk_p	( clk )
fall	( clk , rst )
seq	( clk , rst )
comb	( r , saciClkRising , saciMasterIn , saciRspFall )

Procedures
	synchronize( input: in sl current: in SynchronizerType nextOut: out SynchronizerType )
	synchronize( input: in sl current: in SynchronizerType nextOut: out SynchronizerType )

Constants
SYNCHRONIZER_INIT_0_C	SynchronizerType := ( tmp = > ' 0 ' , sync = > ' 0 ' , last = > ' 0 ' )
SYNCHRONIZER_INIT_1_C	SynchronizerType := ( tmp = > ' 1 ' , sync = > ' 1 ' , last = > ' 1 ' )

Types
StateType	( IDLE_S , CHIP_SELECT_S , TX_S , RX_START_S , RX_HEADER_S , RX_DATA_S , ACK_S )

Signals
r	RegType
rin	RegType
saciRspFall	sl
saciClkCnt	unsigned ( 31 downto 0 )
saciClkCntRst	std_logic
saciClkRising	std_logic
saciClkFalling	std_logic
iSaciClk	std_logic
iSaciClkD	std_logic

Records
SynchronizerType
RegType

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/SaciMasterSync.vhd
• protocols/saci/saci1/rtl/SaciMasterSync.vhd