RstPipeline.rtl Architecture Reference

Architecture >> RstPipeline::rtl

Processes
comb	( r , rstIn )
seq	( clk )
comb	( r , rstIn )
seq	( clk )

Constants
INIT_C	slv ( PIPE_STAGES_G- 1 downto 0 ) := ite ( INIT_G = " 1 " , slvOne ( PIPE_STAGES_G ) , INIT_G )
REG_INIT_C	RegType := ( shift = > INIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType

Attributes
shreg_extract	string
shreg_extract	signal is " NO "
max_fanout	integer
max_fanout	signal is MAX_FANOUT_G

Records
RegType

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The documentation for this design unit was generated from the following files:

• base/general/rtl/RstPipeline.vhd
• build/SRC_VHDL/surf/RstPipeline.vhd