RogueTcpMemory Entity Reference

Inheritance diagram for RogueTcpMemory:

Entities
RogueTcpMemory.RogueTcpMemory	architecture

Libraries
ieee

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned

Ports
clock	in	std_logic
reset	in	std_logic
portNum	in	std_logic_vector ( 15 downto 0 )
araddr	out	std_logic_vector ( 31 downto 0 )
arprot	out	std_logic_vector ( 2 downto 0 )
arvalid	out	std_logic
rready	out	std_logic
arready	in	std_logic
rdata	in	std_logic_vector ( 31 downto 0 )
rresp	in	std_logic_vector ( 1 downto 0 )
rvalid	in	std_logic
awaddr	out	std_logic_vector ( 31 downto 0 )
awprot	out	std_logic_vector ( 2 downto 0 )
awvalid	out	std_logic
wdata	out	std_logic_vector ( 31 downto 0 )
wstrb	out	std_logic_vector ( 3 downto 0 )
wvalid	out	std_logic
bready	out	std_logic
awready	in	std_logic
wready	in	std_logic
bresp	in	std_logic_vector ( 1 downto 0 )
bvalid	in	std_logic

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The documentation for this design unit was generated from the following files:

• axi/simlink/sim/RogueTcpMemory.vhd
• build/SRC_VHDL/surf/RogueTcpMemory.vhd