RogueSideBand Entity Reference

Inheritance diagram for RogueSideBand:

Entities
RogueSideBand.RogueSideBand	architecture

Libraries
ieee

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned

Ports
clock	in	std_logic
reset	in	std_logic
portNum	in	std_logic_vector ( 15 downto 0 )
txOpCode	in	std_logic_vector ( 7 downto 0 )
txOpCodeEn	in	std_logic
txRemData	in	std_logic_vector ( 7 downto 0 )
rxOpCode	out	std_logic_vector ( 7 downto 0 )
rxOpCodeEn	out	std_logic
rxRemData	out	std_logic_vector ( 7 downto 0 )

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The documentation for this design unit was generated from the following files:

• axi/simlink/sim/RogueSideBand.vhd
• build/SRC_VHDL/surf/RogueSideBand.vhd