RoceConfigurator.rtl Architecture Reference

Architecture >> RoceConfigurator::rtl

Processes
comb	( axilReadMaster , axilWriteMaster , mAxisMetaDataReqSlave , r , rst , sAxisMetaDataRespMaster )
seq	( clk )

Constants
REG_INIT_C	RegType := ( metaDataIsSet = > ' 0 ' , metaDataTx = > ( others = > ' 0 ' ) , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , metaDataIsReady = > ' 0 ' , metaDataRx = > ( others = > ' 0 ' ) , txMaster = > AXI_STREAM_MASTER_INIT_C , rxSlave = > AXI_STREAM_SLAVE_INIT_C , state = > IDLE_S )

Types
StateType	( IDLE_S , DUMP_CONFIG_S , GET_RESPONSE_S )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following file:

• ethernet/RoCEv2/rtl/RoceConfigurator.vhd