RegisterVector.rtl Architecture Reference

Architecture >> RegisterVector::rtl

Processes
comb	( en , r , rst , sig_i )
seq	( clk , rst )

Constants
INIT_C	slv ( WIDTH_G- 1 downto 0 ) := ite ( INIT_G = " 0 " , slvZero ( WIDTH_G ) , INIT_G )
REG_INIT_C	RegType := ( reg = > INIT_C )

Signals
r	RegType := REG_INIT_C
rin	RegType

Records
RegType

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The documentation for this design unit was generated from the following file:

• base/general/rtl/RegisterVector.vhd