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Pgp2fcTxCell.Pgp2fcTxCell Architecture Reference
Architecture >> Pgp2fcTxCell::Pgp2fcTxCell

Processes

PROCESS_324  ( schTxDataVc , vc0FrameTxData , vc0FrameTxEOF , vc0FrameTxEOFE , vc0FrameTxSOF , vc0FrameTxValid , vc0RemAlmostFull , vc0Serial , vc1FrameTxData , vc1FrameTxEOF , vc1FrameTxEOFE , vc1FrameTxSOF , vc1FrameTxValid , vc1RemAlmostFull , vc1Serial , vc2FrameTxData , vc2FrameTxEOF , vc2FrameTxEOFE , vc2FrameTxSOF , vc2FrameTxValid , vc2RemAlmostFull , vc2Serial , vc3FrameTxData , vc3FrameTxEOF , vc3FrameTxEOFE , vc3FrameTxSOF , vc3FrameTxValid , vc3RemAlmostFull , vc3Serial )
PROCESS_325  ( pgpTxClk )
PROCESS_326  ( cellCnt , curState , curTypeLast , eocWord , intTimeout , muxFrameTxData , muxFrameTxEOF , muxFrameTxEOFE , muxFrameTxSOF , muxFrameTxValid , muxRemAlmostFull , schTxIdle , schTxReq , socWord )
PROCESS_327  ( pgpTxClk )
PROCESS_328  ( pgpTxClk )

Constants

TX_DATA_C  slv ( 2 downto 0 ) := " 000 "
TX_SOC_C  slv ( 2 downto 0 ) := " 001 "
TX_SOF_C  slv ( 2 downto 0 ) := " 010 "
TX_EOC_C  slv ( 2 downto 0 ) := " 011 "
TX_EOF_C  slv ( 2 downto 0 ) := " 100 "
TX_EOFE_C  slv ( 2 downto 0 ) := " 101 "
TX_CRCA_C  slv ( 2 downto 0 ) := " 110 "
TX_CRCB_C  slv ( 2 downto 0 ) := " 111 "

Types

StateType  ( IDLE_S , EMPTY_S , SOC_S , DATA_S , CRCA_S , CRCB_S , EOC_S )

Signals

muxFrameTxValid  sl
muxFrameTxSOF  sl
muxFrameTxEOF  sl
muxFrameTxEOFE  sl
muxFrameTxData  slv ( 15 downto 0 )
muxRemAlmostFull  sl
cellCnt  slv ( PAYLOAD_CNT_TOP_G downto 0 )
cellCntRst  sl
nxtFrameTxReady  sl
nxtType  slv ( 2 downto 0 )
nxtTypeLast  slv ( 2 downto 0 )
curTypeLast  slv ( 2 downto 0 )
nxtTxSOF  sl
nxtTxEOF  sl
nxtTxAck  sl
nxtData  slv ( 15 downto 0 )
eocWord  slv ( 15 downto 0 )
socWord  slv ( 15 downto 0 )
crcWordA  slv ( 15 downto 0 )
crcWordB  slv ( 15 downto 0 )
serialCntEn  sl
vc0Serial  slv ( 5 downto 0 )
vc1Serial  slv ( 5 downto 0 )
vc2Serial  slv ( 5 downto 0 )
vc3Serial  slv ( 5 downto 0 )
muxSerial  slv ( 5 downto 0 )
dly0Data  slv ( 15 downto 0 ) := ( others = > ' 0 ' )
dly0Type  slv ( 2 downto 0 ) := ( others = > ' 0 ' )
dly1Data  slv ( 15 downto 0 ) := ( others = > ' 0 ' )
dly1Type  slv ( 2 downto 0 ) := ( others = > ' 0 ' )
dly2Data  slv ( 15 downto 0 ) := ( others = > ' 0 ' )
dly2Type  slv ( 2 downto 0 ) := ( others = > ' 0 ' )
dly3Data  slv ( 15 downto 0 ) := ( others = > ' 0 ' )
dly3Type  slv ( 2 downto 0 ) := ( others = > ' 0 ' )
dly4Data  slv ( 15 downto 0 ) := ( others = > ' 0 ' )
dly4Type  slv ( 2 downto 0 ) := ( others = > ' 0 ' )
int0FrameTxReady  sl := ' 0 '
int1FrameTxReady  sl := ' 0 '
int2FrameTxReady  sl := ' 0 '
int3FrameTxReady  sl := ' 0 '
intTimeout  sl := ' 0 '
intOverflow  slv ( 3 downto 0 ) := ( others = > ' 0 ' )
curState  StateType := IDLE_S
nxtState  StateType

The documentation for this design unit was generated from the following file: