Pgp2bTxPhy.Pgp2bTxPhy Architecture Reference

Architecture >> Pgp2bTxPhy::Pgp2bTxPhy

Processes
PROCESS_286	( pgpTxClk )
PROCESS_287	( algnCnt , alnAData , alnADataK , alnBData , alnBDataK , cellData , cellDataK , cellTxEOC , curState , intTxLinkReady , ltsAData , ltsADataK , ltsBData , ltsBDataK , skpAData , skpADataK , skpBData , skpBDataK )
PROCESS_288	( pgpTxClk )
PROCESS_289	( pgpTxClk )

Constants
ST_LOCK_C	slv ( 3 downto 0 ) := " 0000 "
ST_SKP_A_C	slv ( 3 downto 0 ) := " 0001 "
ST_SKP_B_C	slv ( 3 downto 0 ) := " 0010 "
ST_LTS_A_C	slv ( 3 downto 0 ) := " 0011 "
ST_LTS_B_C	slv ( 3 downto 0 ) := " 0100 "
ST_ALN_A_C	slv ( 3 downto 0 ) := " 0101 "
ST_ALN_B_C	slv ( 3 downto 0 ) := " 0110 "
ST_CELL_C	slv ( 3 downto 0 ) := " 0111 "
ST_EMPTY_C	slv ( 3 downto 0 ) := " 1000 "

Signals
algnCnt	slv ( 6 downto 0 ) := ( others = > ' 0 ' )
algnCntRst	sl
intTxLinkReady	sl := ' 0 '
nxtTxLinkReady	sl
nxtTxData	slv ( TX_LANE_CNT_G* 16 - 1 downto 0 )
nxtTxDataK	slv ( TX_LANE_CNT_G* 2 - 1 downto 0 )
dlyTxData	slv ( TX_LANE_CNT_G* 16 - 1 downto 0 ) := ( others = > ' 0 ' )
dlyTxDataK	slv ( TX_LANE_CNT_G* 2 - 1 downto 0 ) := ( others = > ' 0 ' )
dlySelect	sl := ' 0 '
intTxData	slv ( TX_LANE_CNT_G* 16 - 1 downto 0 ) := ( others = > ' 0 ' )
intTxDataK	slv ( TX_LANE_CNT_G* 2 - 1 downto 0 ) := ( others = > ' 0 ' )
intTxOpCode	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
intTxOpCodeEn	sl := ' 0 '
skpAData	slv ( TX_LANE_CNT_G* 16 - 1 downto 0 )
skpADataK	slv ( TX_LANE_CNT_G* 2 - 1 downto 0 )
skpBData	slv ( TX_LANE_CNT_G* 16 - 1 downto 0 )
skpBDataK	slv ( TX_LANE_CNT_G* 2 - 1 downto 0 )
alnAData	slv ( TX_LANE_CNT_G* 16 - 1 downto 0 )
alnADataK	slv ( TX_LANE_CNT_G* 2 - 1 downto 0 )
alnBData	slv ( TX_LANE_CNT_G* 16 - 1 downto 0 )
alnBDataK	slv ( TX_LANE_CNT_G* 2 - 1 downto 0 )
ltsAData	slv ( TX_LANE_CNT_G* 16 - 1 downto 0 )
ltsADataK	slv ( TX_LANE_CNT_G* 2 - 1 downto 0 )
ltsBData	slv ( TX_LANE_CNT_G* 16 - 1 downto 0 )
ltsBDataK	slv ( TX_LANE_CNT_G* 2 - 1 downto 0 )
cellData	slv ( TX_LANE_CNT_G* 16 - 1 downto 0 )
cellDataK	slv ( TX_LANE_CNT_G* 2 - 1 downto 0 )
dlyTxEOC	sl := ' 0 '
curState	slv ( 3 downto 0 ) := ST_LOCK_C
nxtState	slv ( 3 downto 0 )

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The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp2b/core/rtl/Pgp2bTxPhy.vhd