Pgp2bRxPhy.Pgp2bRxPhy Architecture Reference

Architecture >> Pgp2bRxPhy::Pgp2bRxPhy

Processes
PROCESS_283	( pgpRxClk , pgpRxClkRst )
PROCESS_284	( curState , dly1RxDecErr , dly1RxDispErr , ltsCnt , phyRxReady , rxDetectInvert , rxDetectLts , rxDetectLtsOk , stateCnt )
PROCESS_285	( pgpRxClk , pgpRxClkRst )
PROCESS_286	( pgpRxClk , pgpRxClkRst )
PROCESS_287	( dly0RxData , dly0RxDataK , dly0RxDecErr , dly0RxDispErr , dly1RxData , dly1RxDataK , dly1RxDecErr , dly1RxDispErr )

Constants
ST_RESET_C	slv ( 2 downto 0 ) := " 001 "
ST_LOCK_C	slv ( 2 downto 0 ) := " 010 "
ST_WAIT_C	slv ( 2 downto 0 ) := " 011 "
ST_INVRT_C	slv ( 2 downto 0 ) := " 100 "
ST_READY_C	slv ( 2 downto 0 ) := " 101 "

Signals
dly0RxData	slv ( RX_LANE_CNT_G* 16 - 1 downto 0 ) := ( others = > ' 0 ' )
dly0RxDataK	slv ( RX_LANE_CNT_G* 2 - 1 downto 0 ) := ( others = > ' 0 ' )
dly0RxDispErr	slv ( RX_LANE_CNT_G* 2 - 1 downto 0 ) := ( others = > ' 0 ' )
dly0RxDecErr	slv ( RX_LANE_CNT_G* 2 - 1 downto 0 ) := ( others = > ' 0 ' )
dly1RxData	slv ( RX_LANE_CNT_G* 16 - 1 downto 0 ) := ( others = > ' 0 ' )
dly1RxDataK	slv ( RX_LANE_CNT_G* 2 - 1 downto 0 ) := ( others = > ' 0 ' )
dly1RxDispErr	slv ( RX_LANE_CNT_G* 2 - 1 downto 0 ) := ( others = > ' 0 ' )
dly1RxDecErr	slv ( RX_LANE_CNT_G* 2 - 1 downto 0 ) := ( others = > ' 0 ' )
rxDetectLts	sl := ' 0 '
rxDetectLtsOk	sl := ' 0 '
rxDetectLtsRaw	slv ( 1 downto 0 )
rxDetectInvert	slv ( RX_LANE_CNT_G- 1 downto 0 ) := ( others = > ' 0 ' )
rxDetectInvertRaw	slv ( RX_LANE_CNT_G- 1 downto 0 )
rxDetectRemLink	sl := ' 0 '
rxDetectRemData	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
rxDetectOpCodeEn	sl := ' 0 '
rxDetectOpCodeEnRaw	slv ( 1 downto 0 )
rxDetectSOC	sl := ' 0 '
rxDetectSOCRaw	slv ( 1 downto 0 )
rxDetectSOF	sl := ' 0 '
rxDetectSOFRaw	slv ( 1 downto 0 )
rxDetectEOC	sl := ' 0 '
rxDetectEOCRaw	slv ( 1 downto 0 )
rxDetectEOF	sl := ' 0 '
rxDetectEOFRaw	slv ( 1 downto 0 )
rxDetectEOFE	sl := ' 0 '
rxDetectEOFERaw	slv ( 1 downto 0 )
nxtRxLinkReady	sl
stateCntRst	sl
stateCnt	slv ( 19 downto 0 ) := ( others = > ' 0 ' )
ltsCntRst	sl
ltsCntEn	sl
ltsCnt	slv ( 7 downto 0 ) := ( others = > ' 0 ' )
intRxLinkReady	sl := ' 0 '
intRxPolarity	slv ( RX_LANE_CNT_G- 1 downto 0 ) := ( others = > ' 0 ' )
nxtRxPolarity	slv ( RX_LANE_CNT_G- 1 downto 0 )
dlyRxLinkDown	sl := ' 0 '
intRxLinkError	sl := ' 0 '
dlyRxLinkError	sl := ' 0 '
intRxInit	sl := ' 0 '
nxtRxInit	sl
curState	slv ( 2 downto 0 ) := ST_LOCK_C
nxtState	slv ( 2 downto 0 )

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The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp2b/core/rtl/Pgp2bRxPhy.vhd