Pgp2bRxCell.Pgp2bRxCell Architecture Reference

Architecture >> Pgp2bRxCell::Pgp2bRxCell

Processes
PROCESS_277	( pgpRxClk )
PROCESS_278	( dly0Data , dly0SOC )
PROCESS_279	( pgpRxClk )
PROCESS_280	( pgpRxClk )
PROCESS_281	( pgpRxClk )
PROCESS_282	( pgpRxClk )

Signals
dly0SOC	sl
dly0SOF	sl
dly0EOC	sl
dly0EOF	sl
dly0EOFE	sl
dly0Data	slv ( RX_LANE_CNT_G* 16 - 1 downto 0 )
dly1SOC	sl
dly1SOF	sl
dly1EOC	sl
dly1EOF	sl
dly1EOFE	sl
dly1Data	slv ( RX_LANE_CNT_G* 16 - 1 downto 0 )
dly2SOC	sl
dly2SOF	sl
dly2EOC	sl
dly2EOF	sl
dly2EOFE	sl
dly2Data	slv ( RX_LANE_CNT_G* 16 - 1 downto 0 )
dly3SOC	sl
dly3SOF	sl
dly3EOC	sl
dly3EOF	sl
dly3EOFE	sl
dly3Data	slv ( RX_LANE_CNT_G* 16 - 1 downto 0 )
dly4SOC	sl
dly4SOF	sl
dly4EOC	sl
dly4EOF	sl
dly4EOFE	sl
dly4Data	slv ( RX_LANE_CNT_G* 16 - 1 downto 0 )
dly5SOC	sl
dly5SOF	sl
dly5EOC	sl
dly5EOF	sl
dly5EOFE	sl
dly5Data	slv ( RX_LANE_CNT_G* 16 - 1 downto 0 )
dly6SOC	sl
dly6SOF	sl
dly6EOC	sl
dly6EOF	sl
dly6EOFE	sl
dly6Data	slv ( RX_LANE_CNT_G* 16 - 1 downto 0 )
dly7SOC	sl
dly7SOF	sl
dly7EOC	sl
dly7EOF	sl
dly7EOFE	sl
dly7Data	slv ( RX_LANE_CNT_G* 16 - 1 downto 0 )
intCrcRxValid	sl
crcNotZero	sl
linkDownCnt	slv ( 4 downto 0 )
compSOC	sl
compData	slv ( RX_LANE_CNT_G* 16 - 1 downto 0 )
detSOC	sl
detSOF	sl
outData	slv ( RX_LANE_CNT_G* 16 - 1 downto 0 )
detEOC	sl
detEOF	sl
detEOFE	sl
inCellEn	sl
nxtCellEn	sl
inCellSerErr	sl
inCellSOF	sl
inCellEOC	sl
inCellEOF	sl
inCellEOFE	sl
inCellCnt	slv ( PAYLOAD_CNT_TOP_G downto 0 )
vcInFrame	slv ( 3 downto 0 )
currVc	slv ( 1 downto 0 )
serErr	sl
vc0Serial	slv ( 5 downto 0 )
vc0Valid	sl
vc1Serial	slv ( 5 downto 0 )
vc1Valid	sl
vc2Serial	slv ( 5 downto 0 )
vc2Valid	sl
vc3Serial	slv ( 5 downto 0 )
vc3Valid	sl
abortVc	slv ( 1 downto 0 )
abortEn	sl
intCellError	sl
dlyCellError	sl

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The documentation for this design unit was generated from the following file:

• protocols/pgp/pgp2b/core/rtl/Pgp2bRxCell.vhd