MasterAxiStreamTerminateIpIntegrator Entity Reference

Inheritance diagram for MasterAxiStreamTerminateIpIntegrator:

Collaboration diagram for MasterAxiStreamTerminateIpIntegrator:

Entities
MasterAxiStreamTerminateIpIntegrator.mapping	architecture

Libraries
ieee
surf

Use Clauses
std_logic_1164
std_logic_arith
std_logic_unsigned
StdRtlPkg	Package <StdRtlPkg>
AxiStreamPkg	Package <AxiStreamPkg>

Generics
INTERFACENAME	string := " M_AXIS "
HAS_TLAST	natural range 0 to 1 := 1
HAS_TKEEP	natural range 0 to 1 := 1
HAS_TSTRB	natural range 0 to 1 := 0
HAS_TREADY	natural range 0 to 1 := 1
TUSER_WIDTH	natural range 1 to 8 := 2
TID_WIDTH	natural range 1 to 8 := 1
TDEST_WIDTH	natural range 1 to 8 := 1
TDATA_NUM_BYTES	natural range 1 to 128 := 1

Ports
M_AXIS_ACLK	in	std_logic := ' 0 '
M_AXIS_ARESETN	in	std_logic := ' 0 '
M_AXIS_TVALID	out	std_logic
M_AXIS_TDATA	out	std_logic_vector ( ( 8 * TDATA_NUM_BYTES ) - 1 downto 0 )
M_AXIS_TSTRB	out	std_logic_vector ( TDATA_NUM_BYTES- 1 downto 0 )
M_AXIS_TKEEP	out	std_logic_vector ( TDATA_NUM_BYTES- 1 downto 0 )
M_AXIS_TLAST	out	std_logic
M_AXIS_TDEST	out	std_logic_vector ( TDEST_WIDTH- 1 downto 0 )
M_AXIS_TID	out	std_logic_vector ( TID_WIDTH- 1 downto 0 )
M_AXIS_TUSER	out	std_logic_vector ( TUSER_WIDTH- 1 downto 0 )
M_AXIS_TREADY	in	std_logic := ' 1 '

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The documentation for this design unit was generated from the following files:

• axi/axi-stream/ip_integrator/MasterAxiStreamTerminateIpIntegrator.vhd
• build/SRC_VHDL/surf/MasterAxiStreamTerminateIpIntegrator.vhd