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LeapXcvrCore.rtl Architecture Reference
Architecture >> LeapXcvrCore::rtl

Processes

comb  ( axilReadMaster , axilRst , axilWriteMaster , r , regOut )
seq  ( axilClk )

Constants

I2C_SCL_5xFREQ_C  real := 5 . 0 * I2C_SCL_FREQ_G
PRESCALE_C  natural := ( getTimeRatio ( AXIL_CLK_FREQ_G , I2C_SCL_5xFREQ_C ) ) - 1
FILTER_C  natural := natural ( AXIL_CLK_FREQ_G* I2C_MIN_PULSE_G ) + 1
TIMEOUT_C  natural := getTimeRatio ( 40 . 0E - 3 , ( 1 . 0 / AXIL_CLK_FREQ_G ) ) - 1
REG_INIT_C  RegType := ( timer = > 0 , reset = > ' 0 ' , booting = > ' 1 ' , axiRd = > ' 0 ' , txSel = > ' 0 ' , data = > ( others = > ' 0 ' ) , addr = > ( others = > ' 0 ' ) , page = > ( others = > ' 0 ' ) , axilReadSlave = > AXI_LITE_READ_SLAVE_INIT_C , axilWriteSlave = > AXI_LITE_WRITE_SLAVE_INIT_C , regIn = > I2C_REG_MASTER_IN_INIT_C , state = > BOOT_CONFIG_S )

Types

StateType  ( BOOT_CONFIG_S , IDLE_S , PAGE_REQ_S , PAGE_ACK_S , DATA_REQ_S , DATA_ACK_S , WAIT_S )

Signals

r  RegType := REG_INIT_C
rin  RegType
regOut  I2cRegMasterOutType

Records

RegType 

Instantiations

u_i2cregmaster  I2cRegMaster <Entity I2cRegMaster>

The documentation for this design unit was generated from the following file: