Jesd64bTo32b.rtl Architecture Reference

Architecture >> Jesd64bTo32b::rtl

Processes
comb	( data , r , rdRst , trig , valid )
seq	( rdClk )
comb	( data , r , rdRst , trig , valid )
seq	( rdClk )

Constants
REG_INIT_C	RegType := ( rdEn = > ' 0 ' , wordSel = > ' 0 ' , valid = > ' 0 ' , trig = > ' 0 ' , data = > ( others = > ' 0 ' ) )

Signals
r	RegType := REG_INIT_C
rin	RegType
rdEn	sl
valid	sl
trig	slv ( 1 downto 0 )
data	slv ( 63 downto 0 )

Records
RegType

Instantiations
u_fifo	Fifo <Entity Fifo>
u_fifo	Fifo <Entity Fifo>

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/Jesd64bTo32b.vhd
• protocols/jesd204b/rtl/Jesd64bTo32b.vhd