I2cSlave.rtl Architecture Reference

Architecture >> I2cSlave::rtl

Functions
boolean	compaddr1stb ( ibyte: in std_logic_vector( 7 downto 0) )
boolean	compaddr2ndb ( ibyte: in std_logic_vector( 7 downto 0) )
boolean	compaddr1stb ( ibyte: in std_logic_vector( 7 downto 0) )
boolean	compaddr2ndb ( ibyte: in std_logic_vector( 7 downto 0) )

Processes
comb	( i2cSlaveIn , i2ci , r , sRst )
reg	( aRst , clk )
comb	( i2cSlaveIn , i2ci , r , sRst )
reg	( aRst , clk )

Constants
I2C_ADDR_LEN_C	integer := 7 + TENBIT_G* 3
I2C_SLAVE_ADDR_C	std_logic_vector ( ( I2C_ADDR_LEN_C- 1 ) downto 0 ) := conv_std_logic_vector ( I2C_ADDR_G , I2C_ADDR_LEN_C )
I2C_READ_C	std_ulogic := ' 1 '
I2C_WRITE_C	std_ulogic := ' 0 '
OEPOL_LEVEL_C	std_ulogic := conv_std_logic ( OUTPUT_EN_POLARITY_G = 1 )
I2C_LOW_C	std_ulogic := OEPOL_LEVEL_C
I2C_HIZ_C	std_ulogic := not OEPOL_LEVEL_C
I2C_ACK_C	std_ulogic := ' 0 '
TENBIT_ADDR_START_C	std_logic_vector ( 4 downto 0 ) := " 11110 "
REG_INIT_C	i2cslv_reg_type := ( slvstate = > idle , active = > false , addr = > false , sreg = > ( others = > ' 0 ' ) , cnt = > ( others = > ' 0 ' ) , scl = > ' 0 ' , sda = > ' 0 ' , i2ci = > ( others = > ( scl = > ' 0 ' , sda = > ' 0 ' ) ) , scloen = > I2C_HIZ_C , sdaoen = > I2C_HIZ_C , o = > I2C_SLAVE_OUT_INIT_C )

Types
i2c_in_array	( FILTER_G downto 0 ) i2c_in_type
slv_state_type	( idle , checkaddr , check10bitaddr , sclhold , movebyte , handshake )

Signals
r	i2cslv_reg_type := REG_INIT_C
rin	i2cslv_reg_type

Records
i2cslv_reg_type

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The documentation for this design unit was generated from the following files:

• build/SRC_VHDL/surf/I2cSlave.vhd
• protocols/i2c/rtl/I2cSlave.vhd