I2cRegMaster.rtl Architecture Reference

Architecture >> I2cRegMaster::rtl

Functions
integer	getIndex ( endianness: in sl byteCount: in unsigned totalBytes: in unsigned )

Processes
comb	( i2cMasterOut , r , regIn , srst )
seq	( arst , clk )

Constants

REG_INIT_C

RegType := ( state = > WAIT_REQ_S , byteCount = > ( others = > ' 0 ' ) , regOut = > ( regAck = > ' 0 ' , regFail = > ' 0 ' , regFailCode = > ( others = > ' 0 ' ) , regRdData = > ( others = > ' 0 ' ) ) , i2cMasterIn = > ( enable = > ' 0 ' , prescale = > ( others = > ' 0 ' ) , filter = > ( others = > ' 0 ' ) , txnReq = > ' 0 ' , stop = > ' 0 ' , op = > ' 0 ' , busReq = > ' 0 ' , addr = > ( others = > ' 0 ' ) , tenbit = > ' 0 ' , wrValid = > ' 0 ' , wrData = > ( others = > ' 0 ' ) , rdAck = > ' 0 ' ) )

Types
StateType	( WAIT_REQ_S , ADDR_S , WRITE_S , READ_TXN_S , READ_S , BUS_ACK_S , REG_ACK_S )

Signals
r	RegType := REG_INIT_C
rin	RegType
i2cMasterIn	I2cMasterInType
i2cMasterOut	I2cMasterOutType

Records
RegType

Instantiations
i2cmaster_1	I2cMaster <Entity I2cMaster>

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The documentation for this design unit was generated from the following file:

• protocols/i2c/rtl/I2cRegMaster.vhd